mirror of https://github.com/YosysHQ/yosys.git
11 lines
409 B
Plaintext
11 lines
409 B
Plaintext
read_verilog div_mod.v
|
|
hierarchy -top top
|
|
flatten
|
|
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 95 t:EFX_ADD
|
|
select -assert-count 114 t:EFX_LUT4
|
|
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
|