Add dynamic slicing Verilog testcase

2020-03-31 11:51:31 -07:00 · 2020-03-31 11:51:31 -07:00 · 3df66027e0
parent a0cc795e85
commit 3df66027e0
1 changed files with 12 additions and 0 deletions
--- a/tests/simple/dynslice.v
+++ b/tests/simple/dynslice.v
@ -0,0 +1,12 @@
+module dynslice (
+    input clk ,
+    input [9:0] ctrl ,
+    input [15:0] din ,
+    input [3:0] sel ,
+    output reg [127:0] dout
+);
+always @(posedge clk)
+begin
+    dout[ctrl*sel+:16] <= din ;
+end
+endmodule