mirror of https://github.com/YosysHQ/yosys.git
Move from +/shiftx2mux.v into +/techmap.v; cleanup
This commit is contained in:
Eddie Hung
parent
7977574995
commit
8d1b736c4f
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@ -30,4 +30,3 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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$(eval $(call add_share_file,share,techlibs/common/dummy.box))
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$(eval $(call add_share_file,share,techlibs/common/shiftx2mux.v))
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@ -1,38 +0,0 @@
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(* techmap_celltype = /*"$shift*/ "$shiftx" *)
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module _80_shift_shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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genvar i;
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localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
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if (B_WIDTH <= CLOG2_Y_WIDTH+1)
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wire _TECHMAP_FAIL_ = 1;
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// In order to perform this optimisation, this $shiftx must
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// only shift in units of Y_WIDTH, which we check by ensuring
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// that the appropriate LSBs of B are zero
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else if (_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] != {CLOG2_Y_WIDTH{1'b0}})
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wire _TECHMAP_FAIL_ = 1;
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else begin
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// Halve the size of $shiftx by $mux-ing A according to
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// the LSB of B, after discarding the zeroed bits
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wire [(A_WIDTH+Y_WIDTH)/2-1:0] AA;
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for (i = 0; i < (A_WIDTH/Y_WIDTH); i=i+2)
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assign AA[(i/2)*Y_WIDTH +: Y_WIDTH] = B[CLOG2_Y_WIDTH] ? A[(i+1)*Y_WIDTH +: Y_WIDTH] : A[(i+0)*Y_WIDTH +: Y_WIDTH];
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$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+Y_WIDTH)/2'd2), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B({B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}), .Y(Y));
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end
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endgenerate
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endmodule
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@ -129,47 +129,82 @@ module _90_shift_shiftx (A, B, Y);
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
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integer i;
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = 0;
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buffer = {WIDTH{extbit}};
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buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
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if (B_WIDTH > BB_WIDTH) begin
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if (B_SIGNED) begin
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for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
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if (B[i] != B[BB_WIDTH-1])
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overflow = 1;
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end else
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overflow = |B[B_WIDTH-1:BB_WIDTH];
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if (overflow)
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buffer = {WIDTH{extbit}};
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end
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for (i = BB_WIDTH-1; i >= 0; i = i-1)
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if (B[i]) begin
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if (B_SIGNED && i == BB_WIDTH-1)
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buffer = {buffer, {2**i{extbit}}};
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else if (2**i < WIDTH)
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buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{extbit}};
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generate
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`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
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// If $shift/$shiftx only shifts in units of Y_WIDTH
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// (a common pattern created by pmux2shiftx)
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// which is checked by ensuring that all that
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// the appropriate LSBs of B are constant zero,
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// then we can decompose LSB first instead of
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// MSB first
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localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
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if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
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_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
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_TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
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// Halve the size of $shift/$shiftx by $mux-ing A according to
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// the LSB of B, after discarding the zeroed bits
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localparam len = 2**(B_WIDTH-1);
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wire [len-1:0] T, F;
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genvar i;
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for (i = 0; i < A_WIDTH; i=i+Y_WIDTH*2) begin
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assign F[i/2 +: Y_WIDTH] = A[i +: Y_WIDTH];
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assign T[i/2 +: Y_WIDTH] = (i + Y_WIDTH < A_WIDTH) ? A[i+Y_WIDTH +: Y_WIDTH] : {Y_WIDTH{extbit}};
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end
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end
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wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
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wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
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if (_TECHMAP_CELLTYPE_ == "$shift")
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$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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else
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$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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end
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else
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`endif
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begin
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localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
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assign Y = buffer;
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
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integer i;
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = 0;
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buffer = {WIDTH{extbit}};
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buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
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if (B_WIDTH > BB_WIDTH) begin
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if (B_SIGNED) begin
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for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
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if (B[i] != B[BB_WIDTH-1])
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overflow = 1;
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end else
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overflow = |B[B_WIDTH-1:BB_WIDTH];
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if (overflow)
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buffer = {WIDTH{extbit}};
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end
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for (i = BB_WIDTH-1; i >= 0; i = i-1)
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if (B[i]) begin
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if (B_SIGNED && i == BB_WIDTH-1)
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buffer = {buffer, {2**i{extbit}}};
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else if (2**i < WIDTH)
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buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{extbit}};
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end
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end
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assign Y = buffer;
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end
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endgenerate
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endmodule
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@ -74,13 +74,13 @@ design -save gold
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design -load gold
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techmap
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techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
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abc -lut 6
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select -assert-min 17 t:$lut
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design -load gold
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techmap -map +/shiftx2mux.v -map +/techmap.v
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techmap
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abc -lut 6
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select -assert-count 16 t:$lut
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@ -92,13 +92,13 @@ sat -verify -prove-asserts -show-ports miter
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design -load gold
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techmap
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techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
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abc9 -lut 6
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select -assert-min 17 t:$lut
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design -load gold
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techmap -map +/shiftx2mux.v -map +/techmap.v
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techmap
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abc9 -lut 6
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select -assert-count 16 t:$lut
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