Make testcase clearer with \o having its own init

tests/sat/initval.ys

@@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts
 design -reset
 read_verilog -icells <<EOT
 module top(input clk, i, output o, p);
+(* init = 1'b0 *)
+wire o;
 (* init = 1'bx *)
 wire p = o;
 $_DFF_P_ dff (.C(clk), .D(i), .Q(o));