tests: update/extend task argument tests

tests/verilog/bug2042-sv.ys

@@ -0,0 +1,34 @@
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b
+);
+
+    task SomeTaskName(a);
+       b = ~a;
+    endtask
+
+    always @*
+        SomeTaskName(a);
+
+    assert property (b == ~a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT

tests/verilog/bug2042.ys

@@ -1,4 +1,4 @@
-logger -expect error "Non-ANSI style task/function arguments not currently supported" 1
+logger -expect error "task/function argument direction missing" 1
 read_verilog <<EOT
 module Task_Test_Top
 (
@@ -9,4 +9,3 @@ module Task_Test_Top
 
 endmodule
 EOT
-