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Disable RAM16X1D test

This commit is contained in:
Eddie Hung 2019-12-13 10:28:13 -08:00
parent c3262d6075
commit a5764a1236
1 changed files with 17 additions and 17 deletions
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34
tests/arch/xilinx/lutram.ys
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@ -1,20 +1,20 @@
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 4
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 8 t:RAM16X1D
select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
#read_verilog ../common/lutram.v
#hierarchy -top lutram_1w1r -chparam A_WIDTH 4
#proc
#memory -nomap
#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
#memory
#opt -full
#
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
#
#design -load postopt
#cd lutram_1w1r
#select -assert-count 1 t:BUFG
#select -assert-count 8 t:FDRE
#select -assert-count 8 t:RAM16X1D
#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
design -reset