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add tristate buffer and test
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@ -302,6 +302,12 @@ module OBUF(output O, input I);
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assign O = I;
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endmodule
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module TBUF (O, I, OEN);
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input I, OEN;
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output O;
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assign O = OEN ? I : 1'bz;
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endmodule
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module GSR (input GSRI);
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wire GSRO = GSRI;
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endmodule
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@ -174,7 +174,7 @@ struct SynthGowinPass : public ScriptPass
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run("synth -run coarse");
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}
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/gowin/bram.txt");
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run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
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@ -230,7 +230,7 @@ struct SynthGowinPass : public ScriptPass
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run("techmap -map +/gowin/cells_map.v");
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run("setundef -undriven -params -zero");
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run("hilomap -singleton -hicell VCC V -locell GND G");
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run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
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run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)");
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run("dffinit -ff DFF Q INIT");
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run("clean");
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@ -0,0 +1,13 @@
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read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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#Internal cell type used. Need support it.
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select -assert-count 1 t:TBUF
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select -assert-count 2 t:IBUF
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select -assert-none t:TBUF t:IBUF %% t:* %D
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