riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

do not use wide luts in testcase

This commit is contained in:
Pepijn de Vos 2019-10-28 14:40:12 +01:00
parent 4ec4d5ec7e
commit 9517525224
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tests/arch/gowin/mux.ys
View File

@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
@ -27,7 +27,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
@ -39,7 +39,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 10 t:LUT4