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Merge blockram tests

This commit is contained in:
Eddie Hung 2019-12-16 13:01:51 -08:00
parent d910bec8e0
commit e990c013c5
3 changed files with 81 additions and 47 deletions
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0
tests/arch/common/blockram_params.v → tests/arch/common/blockram.v
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tests/arch/xilinx/blockram.ys Normal file
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### TODO: Not running equivalence checking because BRAM models does not exists
### currently. Checking instance counts instead.
## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
#read_verilog ../common/blockram.v
#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
#synth_xilinx -top sync_ram_sdp
#cd sync_ram_sdp
#select -assert-count 1 t:RAMB18E1
#
#design -reset
#read_verilog ../common/blockram.v
#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
#synth_xilinx -top sync_ram_sdp
#cd sync_ram_sdp
#select -assert-count 1 t:RAMB18E1
#
#design -reset
#read_verilog ../common/blockram.v
#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
#synth_xilinx -top sync_ram_sdp
#cd sync_ram_sdp
#select -assert-count 1 t:RAMB18E1
#
#design -reset
#read_verilog ../common/blockram.v
#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
#synth_xilinx -top sync_ram_sdp
#cd sync_ram_sdp
#select -assert-count 1 t:RAMB18E1
#
## Anything memory bits < 1024 -> LUTRAM
#design -reset
#read_verilog ../common/blockram.v
#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
#synth_xilinx -top sync_ram_sdp
#cd sync_ram_sdp
#select -assert-count 0 t:RAMB18E1
#select -assert-count 4 t:RAM128X1D
#
## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
#design -reset
#read_verilog ../common/blockram.v
#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
#synth_xilinx -top sync_ram_sdp
#cd sync_ram_sdp
#select -assert-count 1 t:RAMB36E1
#
#
#### With parameters
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
setattr -set ram_block 1 m:memory
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
setattr -set logic_block 1 m:memory
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1

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tests/arch/xilinx/blockram_params.ys
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## TODO: Not running equivalence checking because BRAM models does not exists
## currently. Checking instance counts instead.
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
# Anything memory bits < 1024 -> LUTRAM
design -reset
read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1
select -assert-count 4 t:RAM128X1D
# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
design -reset
read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB36E1