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update test
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@ -34,11 +34,12 @@ proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFS
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select -assert-count 1 t:DFF
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select -assert-count 1 t:LUT2
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
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select -assert-none t:DFF t:LUT2 t:IBUF t:OBUF %% t:* %D
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design -load read
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