riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fixed error

This commit is contained in:
Miodrag Milanovic 2019-10-18 13:15:36 +02:00
parent 9bd9db56c8
commit 190b40341a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tests/arch/common/counter.v
View File

@ -6,6 +6,6 @@ module top ( out, clk, reset );
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
end
else
out <= out + 1;
endmodule