Merge remote-tracking branch 'origin/master' into xc7dsp

passes/pmgen/peepopt_dffmux.pmg

@@ -42,6 +42,12 @@ code
 		rst = port(rstmux, rstmuxBA).as_const();
 	int width = GetSize(D);
 
+	SigSpec &ceA = cemux->connections_.at(\A);
+	SigSpec &ceB = cemux->connections_.at(\B);
+	SigSpec &ceY = cemux->connections_.at(\Y);
+	SigSpec &dffD = dff->connections_.at(\D);
+	SigSpec &dffQ = dff->connections_.at(\Q);
+
 	if (D[width-1] == D[width-2]) {
 		did_something = true;
 
@@ -61,12 +67,12 @@ code
 			}
 		}
 
-		cemux->connections_.at(\A).remove(i, width-i);
-		cemux->connections_.at(\B).remove(i, width-i);
-		cemux->connections_.at(\Y).remove(i, width-i);
+		ceA.remove(i, width-i);
+		ceB.remove(i, width-i);
+		ceY.remove(i, width-i);
 		cemux->fixup_parameters();
-		dff->connections_.at(\D).remove(i, width-i);
-		dff->connections_.at(\Q).remove(i, width-i);
+		dffD.remove(i, width-i);
+		dffQ.remove(i, width-i);
 		dff->fixup_parameters();
 
 		log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
@@ -88,11 +94,11 @@ code
 			if (init == State::Sx || init == D[i].data) {
 				count++;
 				module->connect(Q[i], D[i]);
-				cemux->connections_.at(\A).remove(i);
-				cemux->connections_.at(\B).remove(i);
-				cemux->connections_.at(\Y).remove(i);
-				dff->connections_.at(\D).remove(i);
-				dff->connections_.at(\Q).remove(i);
+				ceA.remove(i);
+				ceB.remove(i);
+				ceY.remove(i);
+				dffD.remove(i);
+				dffQ.remove(i);
 			}
 		}
 		if (count > 0) {

passes/pmgen/peepopt_shiftmul.pmg

@@ -50,9 +50,8 @@ code
 	if (GetSize(const_factor_cnst) > 20)
 		reject;
 
-	if (shift->type.in($shift, $shiftx))
-		if (GetSize(port(shift, \Y)) > const_factor)
-			reject;
+	if (GetSize(port(shift, \Y)) > const_factor)
+		reject;
 
 	int factor_bits = ceil_log2(const_factor);
 	SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);

tests/various/peepopt.ys

@@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
 design -reset
 read_verilog <<EOT
 module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
-assign y = 1'b1 >> (w * (8'b110));
+assign y = 1'b1 >> (w * (3'b110));
 endmodule
 EOT
 
@@ -25,7 +25,31 @@ equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shr
-select -assert-count 0 t:$mul
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
+	assign Y = D >> (S*3);
+endmodule
+EOT
+
+prep
+design -save gold
+peepopt
+design -stash gate
+
+design -import gold -as gold peepopt_shiftmul_2
+design -import gate -as gate peepopt_shiftmul_2
+
+miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
+sat -show-public -enable_undef -prove-asserts miter
+cd gate
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
 select -assert-count 0 t:$shr t:$mul %% t:* %D
 
 ####################