mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
This commit is contained in:
Eddie Hung
GitHub
commit
b66c99ece0
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@ -985,7 +985,7 @@ void AigerReader::post_process()
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// operate (and run checks on) this one module
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RTLIL::Design *mapped_design = new RTLIL::Design;
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mapped_design->add(module);
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Pass::call(mapped_design, "clean -purge");
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Pass::call(mapped_design, "clean");
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mapped_design->modules_.erase(module->name);
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delete mapped_design;
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@ -27,6 +27,7 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
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PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg
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PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
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PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg
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passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
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@ -60,6 +60,7 @@ struct PeepoptPass : public Pass {
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peepopt_pm pm(module, module->selected_cells());
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pm.run_shiftmul();
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pm.run_muldiv();
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pm.run_dffmux();
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}
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}
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}
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@ -0,0 +1,113 @@
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pattern dffmux
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state <IdString> cemuxAB rstmuxBA
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state <SigSpec> sigD
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match dff
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select dff->type == $dff
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select GetSize(port(dff, \D)) > 1
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endmatch
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match rstmux
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select rstmux->type == $mux
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select GetSize(port(rstmux, \Y)) > 1
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index <SigSpec> port(rstmux, \Y) === port(dff, \D)
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choice <IdString> BA {\B, \A}
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select port(rstmux, BA).is_fully_const()
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set rstmuxBA BA
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optional
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endmatch
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code sigD
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if (rstmux)
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sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
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else
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sigD = port(dff, \D);
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endcode
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match cemux
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select cemux->type == $mux
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select GetSize(port(cemux, \Y)) > 1
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index <SigSpec> port(cemux, \Y) === sigD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(cemux, AB) === port(dff, \Q)
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set cemuxAB AB
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endmatch
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code
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SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
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SigSpec Q = port(dff, \Q);
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Const rst;
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if (rstmux)
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rst = port(rstmux, rstmuxBA).as_const();
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int width = GetSize(D);
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SigSpec &ceA = cemux->connections_.at(\A);
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SigSpec &ceB = cemux->connections_.at(\B);
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SigSpec &ceY = cemux->connections_.at(\Y);
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SigSpec &dffD = dff->connections_.at(\D);
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SigSpec &dffQ = dff->connections_.at(\Q);
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if (D[width-1] == D[width-2]) {
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did_something = true;
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SigBit sign = D[width-1];
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bool is_signed = sign.wire;
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int i;
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for (i = width-1; i >= 2; i--) {
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if (!is_signed) {
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module->connect(Q[i], sign);
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if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
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break;
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}
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else {
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module->connect(Q[i], Q[i-1]);
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if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
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break;
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}
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}
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ceA.remove(i, width-i);
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ceB.remove(i, width-i);
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ceY.remove(i, width-i);
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cemux->fixup_parameters();
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dffD.remove(i, width-i);
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dffQ.remove(i, width-i);
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dff->fixup_parameters();
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log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
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accept;
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}
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else {
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int count = 0;
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for (int i = width-1; i >= 0; i--) {
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if (D[i].wire)
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continue;
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Wire *w = Q[i].wire;
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auto it = w->attributes.find(\init);
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State init;
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if (it != w->attributes.end())
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init = it->second[Q[i].offset];
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else
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init = State::Sx;
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if (init == State::Sx || init == D[i].data) {
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count++;
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module->connect(Q[i], D[i]);
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ceA.remove(i);
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ceB.remove(i);
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ceY.remove(i);
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dffD.remove(i);
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dffQ.remove(i);
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}
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}
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if (count > 0) {
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did_something = true;
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cemux->fixup_parameters();
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dff->fixup_parameters();
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log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
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}
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accept;
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}
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endcode
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@ -1,13 +0,0 @@
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module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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module peepopt_shiftmul_1 (output y, input [2:0] w);
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assign y = 1'b1 >> (w * (3'b110));
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endmodule
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module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
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wire [3:0] t;
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assign t = i * 3;
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assign o = t / 3;
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endmodule
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@ -0,0 +1,175 @@
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read_verilog <<EOT
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module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shiftx
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select -assert-count 0 t:$shiftx t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
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assign y = 1'b1 >> (w * (3'b110));
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
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assign Y = D >> (S*3);
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endmodule
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EOT
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prep
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftmul_2
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design -import gate -as gate peepopt_shiftmul_2
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -show-public -enable_undef -prove-asserts miter
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cd gate
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
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wire [3:0] t;
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assign t = i * 3;
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assign o = t / 3;
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 0 t:*
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=5 %i
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select -assert-count 1 t:$mux r:WIDTH=5 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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wreduce
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 2 t:$mux
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select -assert-count 2 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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wreduce
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 2 t:$mux
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select -assert-count 2 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
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