test: add failing test

2020-05-04 12:18:02 -07:00 · 2020-05-04 12:18:02 -07:00 · 2e911bc806
parent 584780d776
commit 2e911bc806
1 changed files with 5 additions and 0 deletions
--- a/tests/verilog/upto.ys
+++ b/tests/verilog/upto.ys
@ -0,0 +1,5 @@
+read_verilog <<EOT
+module top(input [-128:-65] a);
+endmodule
+EOT
+dump