add testcase for #1614

2020-02-03 21:29:54 +01:00 · 2020-02-03 21:29:54 +01:00 · 90c78f1f85
parent b844b078db
commit 90c78f1f85
1 changed files with 5 additions and 0 deletions
--- a/tests/various/bug1614.ys
+++ b/tests/various/bug1614.ys
@ -0,0 +1,5 @@
+read_verilog <<EOT
+module testcase;
+    wire [3:0] #1 a = 4'b0000;
+endmodule
+EOT