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check ff's separately

This commit is contained in:
Miodrag Milanovic 2019-10-04 11:00:49 +02:00
parent 3d3479b0af
commit 91ad3ab717
2 changed files with 14 additions and 26 deletions
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22
tests/anlogic/dffs.v
View File

@ -13,25 +13,3 @@ module dffe
if ( en )
q <= d;
endmodule
module top (
input clk,
input en,
input a,
output b,b1,
);
dff u_dff (
.clk (clk ),
.d (a ),
.q (b )
);
dffe u_ndffe (
.clk (clk ),
.en (en),
.d (a ),
.q (b1 )
);
endmodule

18
tests/anlogic/dffs.ys
View File

@ -1,10 +1,20 @@
read_verilog dffs.v
hierarchy -top top
design -save read
proc
flatten
hierarchy -top dff
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
proc
hierarchy -top dffe
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 2 t:AL_MAP_SEQ
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D