diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v
index d97840c43..3418787c9 100644
--- a/tests/anlogic/dffs.v
+++ b/tests/anlogic/dffs.v
@@ -13,25 +13,3 @@ module dffe
 		if ( en )
 			q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys
index a15c6f24e..38dffa326 100644
--- a/tests/anlogic/dffs.ys
+++ b/tests/anlogic/dffs.ys
@@ -1,10 +1,20 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_SEQ %% t:* %D
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:AL_MAP_LUT3
-select -assert-count 2 t:AL_MAP_SEQ
+select -assert-count 1 t:AL_MAP_SEQ
 select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D