Add quick test

2019-09-30 15:34:04 -07:00 · 2019-09-30 15:34:04 -07:00 · 8b239ee707
parent f2f19df2d4
commit 8b239ee707
1 changed files with 10 additions and 0 deletions
--- a/tests/techmap/aigmap.ys
+++ b/tests/techmap/aigmap.ys
@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, j, s, output o, p);
+assign o = s ? j : i;
+assign p = ~i;
+endmodule
+EOT
+
+select t:$mux
+aigmap -select
+select -assert-any %