Make SV2017 compliant courtesy of @wsnyder

2019-12-12 07:34:07 -08:00 · 2019-12-12 07:34:07 -08:00 · 23fcfd0adb
parent 2666482282
commit 23fcfd0adb
1 changed files with 1 additions and 3 deletions
--- a/tests/simple/mem_arst.v
+++ b/tests/simple/mem_arst.v
@ -7,11 +7,9 @@ module MyMem #(
  input                  Clk_i,
  input  [AddrWidth-1:0] Addr_i,
  input  [DataWidth-1:0] Data_i,
-  output [DataWidth-1:0] Data_o,
+  output reg [DataWidth-1:0] Data_o,
  input                  WR_i);

-  reg [DataWidth-1:0] Data_o;
-
  localparam Size = 2**AddrWidth;

  (* mem2reg *)