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hierarchy - proc reorder

This commit is contained in:
Miodrag Milanovic 2019-10-18 09:06:43 +02:00
parent 03a3deec43
commit 46af9a0ff7
4 changed files with 10 additions and 9 deletions
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1
tests/anlogic/add_sub.ys
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@ -1,5 +1,6 @@
read_verilog add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

4
tests/anlogic/dffs.ys
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@ -1,8 +1,8 @@
read_verilog dffs.v
design -save read
proc
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
proc
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module

6
tests/anlogic/latches.ys
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@ -1,8 +1,8 @@
read_verilog latches.v
design -save read
proc
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchp # Constrain all select calls below inside the top module
@ -12,8 +12,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D
design -load read
proc
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchn # Constrain all select calls below inside the top module
@ -23,8 +23,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D
design -load read
proc
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchsr # Constrain all select calls below inside the top module

8
tests/anlogic/mux.ys
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@ -1,8 +1,8 @@
read_verilog mux.v
design -save read
proc
hierarchy -top mux2
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
@ -11,8 +11,8 @@ select -assert-count 1 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_LUT3 %% t:* %D
design -load read
proc
hierarchy -top mux4
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
@ -21,8 +21,8 @@ select -assert-count 1 t:AL_MAP_LUT6
select -assert-none t:AL_MAP_LUT6 %% t:* %D
design -load read
proc
hierarchy -top mux8
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
@ -32,8 +32,8 @@ select -assert-count 1 t:AL_MAP_LUT6
select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D
design -load read
proc
hierarchy -top mux16
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module