Add testcase for #2010

2020-05-01 14:07:33 -07:00 · 2020-05-01 14:07:33 -07:00 · 7f9ecddb7f
parent 8ee32adac3
commit 7f9ecddb7f
1 changed files with 10 additions and 0 deletions
--- a/tests/opt/bug2010.ys
+++ b/tests/opt/bug2010.ys
@ -0,0 +1,10 @@
+read_verilog <<EOT
+module test (
+        input signed [1:0] n,
+        output [3:0] dout
+);
+        assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+equiv_opt -assert opt -fine