Use built-in async2sync call as per #1417

2019-09-30 14:56:19 -07:00 · 2019-09-30 14:56:19 -07:00 · 8422ad3e3a
parent 5b7bc3ab85
commit 8422ad3e3a
1 changed files with 0 additions and 4 deletions
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@ -4,11 +4,7 @@ design -save read
 proc
 async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-synth_xilinx
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-design -load read

 synth_xilinx
 flatten