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Update mul test to DSP48E1

This commit is contained in:
Eddie Hung 2019-09-30 14:38:06 -07:00 committed by Miodrag Milanovic
parent 08bd1816e3
commit 5b7bc3ab85
1 changed files with 2 additions and 9 deletions
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11
tests/xilinx/mul.ys
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@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 1 t:LUT5
select -assert-count 33 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 1 t:MUXF7
select -assert-count 12 t:XORCY
select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D