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Remove stat

This commit is contained in:
Eddie Hung 2019-09-18 12:44:34 -07:00
parent f7dbfef792
commit c663a3680b
1 changed files with 0 additions and 1 deletions
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tests/xilinx/mul_unsigned.ys
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@ -4,7 +4,6 @@ hierarchy -top mul_unsigned
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 30 t:FDRE