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verilog: improve specify support when not in -specify mode
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@ -1043,7 +1043,7 @@ list_of_specparam_assignments:
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specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
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specparam_assignment:
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ignspec_id '=' constant_mintypmax_expression ;
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ignspec_id '=' ignspec_expr ;
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ignspec_opt_cond:
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TOK_IF '(' ignspec_expr ')' | /* empty */;
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@ -1060,13 +1060,15 @@ simple_path_declaration :
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;
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path_delay_value :
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'(' path_delay_expression list_of_path_delay_extra_expressions ')'
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| path_delay_expression
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| path_delay_expression list_of_path_delay_extra_expressions
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'(' ignspec_expr list_of_path_delay_extra_expressions ')'
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| ignspec_expr
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| ignspec_expr list_of_path_delay_extra_expressions
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;
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list_of_path_delay_extra_expressions :
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',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
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',' ignspec_expr
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| ',' ignspec_expr list_of_path_delay_extra_expressions
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;
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specify_edge_identifier :
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TOK_POSEDGE | TOK_NEGEDGE ;
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@ -1120,14 +1122,6 @@ system_timing_args :
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system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
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system_timing_args ',' system_timing_arg ;
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path_delay_expression :
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ignspec_constant_expression;
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constant_mintypmax_expression :
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ignspec_constant_expression
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| ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
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;
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// for the time being this is OK, but we may write our own expr here.
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// as I'm not sure it is legal to use a full expr here (probably not)
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// On the other hand, other rules requiring constant expressions also use 'expr'
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@ -7,11 +7,9 @@ module test (
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if (EN) Q <= D;
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specify
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`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
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if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
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$setup(D, posedge CLK &&& EN, 5);
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$hold(posedge CLK, D &&& EN, 6);
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`endif
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endspecify
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endmodule
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@ -55,4 +55,4 @@ equiv_induct -seq 5
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equiv_status -assert
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design -reset
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read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
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read_verilog specify.v
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