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verilog: improve specify support when not in -specify mode

This commit is contained in:
Eddie Hung 2020-02-13 13:27:15 -08:00
parent 2e51dc1856
commit 6b58c1820c
3 changed files with 8 additions and 16 deletions
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20
frontends/verilog/verilog_parser.y
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@ -1043,7 +1043,7 @@ list_of_specparam_assignments:
specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
specparam_assignment:
ignspec_id '=' constant_mintypmax_expression ;
ignspec_id '=' ignspec_expr ;
ignspec_opt_cond:
TOK_IF '(' ignspec_expr ')' | /* empty */;
@ -1060,13 +1060,15 @@ simple_path_declaration :
;
path_delay_value :
'(' path_delay_expression list_of_path_delay_extra_expressions ')'
| path_delay_expression
| path_delay_expression list_of_path_delay_extra_expressions
'(' ignspec_expr list_of_path_delay_extra_expressions ')'
| ignspec_expr
| ignspec_expr list_of_path_delay_extra_expressions
;
list_of_path_delay_extra_expressions :
',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
',' ignspec_expr
| ',' ignspec_expr list_of_path_delay_extra_expressions
;
specify_edge_identifier :
TOK_POSEDGE | TOK_NEGEDGE ;
@ -1120,14 +1122,6 @@ system_timing_args :
system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
system_timing_args ',' system_timing_arg ;
path_delay_expression :
ignspec_constant_expression;
constant_mintypmax_expression :
ignspec_constant_expression
| ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
;
// for the time being this is OK, but we may write our own expr here.
// as I'm not sure it is legal to use a full expr here (probably not)
// On the other hand, other rules requiring constant expressions also use 'expr'

2
tests/various/specify.v
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@ -7,11 +7,9 @@ module test (
if (EN) Q <= D;
specify
`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
`endif
endspecify
endmodule

2
tests/various/specify.ys
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@ -55,4 +55,4 @@ equiv_induct -seq 5
equiv_status -assert
design -reset
read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
read_verilog specify.v