riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

verilog: ignore '&&&' when not in -specify mode

This commit is contained in:
Eddie Hung 2020-02-13 13:06:13 -08:00
parent b523ecf2f4
commit 2e51dc1856
3 changed files with 12 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
frontends/verilog/verilog_lexer.l
View File

@ -440,7 +440,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
}
"&&&" {
if (!specify_mode) REJECT;
if (!specify_mode) return TOK_IGNORED_SPECIFY_AND;
return TOK_SPECIFY_AND;
}

9
frontends/verilog/verilog_parser.y
View File

@ -146,7 +146,7 @@ struct specify_rise_fall {
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
%token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND
%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@ -1117,6 +1117,7 @@ system_timing_arg :
system_timing_args :
system_timing_arg |
system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
system_timing_args ',' system_timing_arg ;
path_delay_expression :
@ -1137,9 +1138,9 @@ ignspec_constant_expression:
ignspec_expr:
expr { delete $1; } |
expr ':' expr ':' expr {
delete $1;
delete $3;
delete $5;
delete $1;
delete $3;
delete $5;
};
ignspec_id:

6
tests/various/specify.v
View File

@ -51,3 +51,9 @@ specify
$setuphold(d, posedge clk, 1:2:3, 4:5:6);
endspecify
endmodule
module test5(input clk, d, e, output q);
specify
$setup(d, posedge clk &&& e, 1:2:3);
endspecify
endmodule