mirror of https://github.com/YosysHQ/yosys.git
ast: Fix handling of identifiers in the global scope
Signed-off-by: David Shah <dave@ds0.me>
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@ -1153,6 +1153,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire)
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{
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current_ast = ast;
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current_ast_mod = nullptr;
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flag_dump_ast1 = dump_ast1;
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flag_dump_ast2 = dump_ast2;
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flag_no_dump_ptr = no_dump_ptr;
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@ -1219,6 +1220,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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}
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design->add(process_module(*it, defer));
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current_ast_mod = nullptr;
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}
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else if ((*it)->type == AST_PACKAGE) {
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// process enum/other declarations
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@ -1169,7 +1169,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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// annotate identifiers using scope resolution and create auto-wires as needed
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if (type == AST_IDENTIFIER) {
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if (current_scope.count(str) == 0) {
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for (auto node : current_ast_mod->children) {
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AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
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for (auto node : current_scope_ast->children) {
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//log("looking at mod scope child %s\n", type2str(node->type).c_str());
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switch (node->type) {
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case AST_PARAMETER:
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@ -1203,7 +1204,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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}
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}
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if (current_scope.count(str) == 0) {
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if (flag_autowire || str == "\\$global_clock") {
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if (current_ast_mod == nullptr) {
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log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared outside of a module.\n", str.c_str());
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} else if (flag_autowire || str == "\\$global_clock") {
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AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
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auto_wire->str = str;
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current_ast_mod->children.push_back(auto_wire);
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@ -0,0 +1,18 @@
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read_verilog -sv <<EOT
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parameter A = 10;
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parameter B = A;
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typedef enum {
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CONST_A = A,
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CONST_B = A+1
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} enum_t;
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module top(output [3:0] q, output [3:0] r);
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assign q = 10;
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assign r = CONST_B;
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endmodule
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EOT
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hierarchy -top top
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sat -verify -prove q 10 top
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sat -verify -prove r 11 top
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