mirror of https://github.com/YosysHQ/yosys.git
xilinx: Initial support for LUT4 devices.
Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
This commit is contained in:
Marcin Kościelnicki
Marcelina Kościelnicka
parent
1f54b0008f
commit
d48950d92d
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@ -34,6 +34,12 @@ module _80_xilinx_lcu (P, G, CI, CO);
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genvar i;
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`ifdef _EXPLICIT_CARRY
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localparam EXPLICIT_CARRY = 1'b1;
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`else
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localparam EXPLICIT_CARRY = 1'b0;
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`endif
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generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
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wire [WIDTH-1:0] C = {CO, CI};
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wire [WIDTH-1:0] S = P & ~G;
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@ -47,7 +53,7 @@ module _80_xilinx_lcu (P, G, CI, CO);
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);
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end endgenerate
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`else
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end else begin
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localparam CARRY4_COUNT = (WIDTH + 3) / 4;
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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@ -79,7 +85,7 @@ module _80_xilinx_lcu (P, G, CI, CO);
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);
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end
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end endgenerate
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`endif
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end endgenerate
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endmodule
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@ -116,9 +122,34 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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genvar i;
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`ifdef _EXPLICIT_CARRY
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localparam EXPLICIT_CARRY = 1'b1;
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`else
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localparam EXPLICIT_CARRY = 1'b0;
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`endif
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generate if (`LUT_SIZE == 4) begin
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wire [Y_WIDTH-1:0] C = {CO, CI};
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wire [Y_WIDTH-1:0] S = {AA ^ BB};
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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MUXCY muxcy (
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.CI(C[i]),
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.DI(AA[i]),
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.S(S[i]),
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.O(CO[i])
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);
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XORCY xorcy (
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.CI(C[i]),
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.LI(S[i]),
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.O(Y[i])
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);
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end endgenerate
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end else if (EXPLICIT_CARRY) begin
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wire [Y_WIDTH-1:0] S = AA ^ BB;
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wire [Y_WIDTH-1:0] DI = AA & BB;
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wire CINIT;
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// Carry chain.
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@ -138,7 +169,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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generate for (i = 0; i < 1; i = i + 1) begin:slice
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CARRY0 #(.CYINIT_FABRIC(1)) carry(
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.CI_INIT(CI),
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.DI(DI[0]),
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.DI(AA[0]),
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.S(S[0]),
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.CO_CHAIN(CO_CHAIN[0]),
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.CO_FABRIC(CO[0]),
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@ -150,7 +181,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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if(i % 4 == 0) begin
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CARRY0 carry (
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.CI(C[i]),
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.DI(DI[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.CO_FABRIC(CO[i]),
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@ -161,7 +192,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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begin
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CARRY carry (
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.CI(C[i]),
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.DI(DI[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.CO_FABRIC(CO[i]),
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@ -174,7 +205,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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if(i % 4 == 0) begin
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CARRY0 top_of_carry (
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.CI(C[i]),
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.DI(DI[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.O(Y[i])
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@ -184,7 +215,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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begin
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CARRY top_of_carry (
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.CI(C[i]),
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.DI(DI[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.O(Y[i])
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@ -213,14 +244,14 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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end
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end endgenerate
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`else
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end else begin
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localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
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wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
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wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
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wire [MAX_WIDTH-1:0] O;
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wire [MAX_WIDTH-1:0] C;
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@ -251,7 +282,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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end
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end endgenerate
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`endif
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end endgenerate
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assign X = S;
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endmodule
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@ -51,43 +51,45 @@ module \$lut (A, Y);
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]));
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end else
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if (WIDTH == 5) begin
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if (WIDTH == 5 && WIDTH <= `LUT_WIDTH) begin
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LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]));
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end else
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if (WIDTH == 6) begin
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if (WIDTH == 6 && WIDTH <= `LUT_WIDTH) begin
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LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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end else
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if (WIDTH == 5 && WIDTH > `LUT_WIDTH) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
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\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
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MUXF5 mux5(.I0(f0), .I1(f1), .S(A[4]), .O(Y));
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end else
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if (WIDTH == 6 && WIDTH > `LUT_WIDTH) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
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\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
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MUXF6 mux6(.I0(f0), .I1(f1), .S(A[5]), .O(Y));
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end else
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if (WIDTH == 7) begin
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wire T0, T1;
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LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
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wire f0, f1;
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\$lut #(.LUT(LUT[ 63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
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\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
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MUXF7 mux7(.I0(f0), .I1(f1), .S(A[6]), .O(Y));
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end else
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if (WIDTH == 8) begin
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wire T0, T1, T2, T3, T4, T5;
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LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
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MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
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MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
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wire f0, f1;
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\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
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\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
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MUXF8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y));
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end else
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if (WIDTH == 9) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[255: 0]), .WIDTH(8)) lut0 (.A(A[7:0]), .Y(f0));
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\$lut #(.LUT(LUT[511:256]), .WIDTH(8)) lut1 (.A(A[7:0]), .Y(f1));
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MUXF9 mux9(.I0(f0), .I1(f1), .S(A[8]), .O(Y));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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@ -49,10 +49,25 @@ struct SynthXilinxPass : public ScriptPass
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc6s}\n");
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log(" -family <family>\n");
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log(" run synthesis for the specified Xilinx architecture\n");
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log(" generate the synthesis netlist for the specified family.\n");
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log(" default: xc7\n");
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log(" supported values:\n");
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log(" - xcup: Ultrascale Plus\n");
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log(" - xcu: Ultrascale\n");
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log(" - xc7: Series 7 (default)\n");
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log(" - xc6s: Spartan 6\n");
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log(" - xc6v: Virtex 6\n");
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log(" - xc5v: Virtex 5 (EXPERIMENTAL)\n");
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log(" - xc4v: Virtex 4 (EXPERIMENTAL)\n");
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log(" - xc3sda: Spartan 3A DSP (EXPERIMENTAL)\n");
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log(" - xc3sa: Spartan 3A (EXPERIMENTAL)\n");
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log(" - xc3se: Spartan 3E (EXPERIMENTAL)\n");
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log(" - xc3s: Spartan 3 (EXPERIMENTAL)\n");
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log(" - xc2vp: Virtex 2 Pro (EXPERIMENTAL)\n");
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log(" - xc2v: Virtex 2 (EXPERIMENTAL)\n");
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log(" - xcve: Virtex E, Spartan 2E (EXPERIMENTAL)\n");
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log(" - xcv: Virtex, Spartan 2 (EXPERIMENTAL)\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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@ -82,10 +97,10 @@ struct SynthXilinxPass : public ScriptPass
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log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
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log(" do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not use DSP48E1s to implement multipliers and associated logic\n");
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log(" do not use DSP48*s to implement multipliers and associated logic\n");
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log("\n");
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log(" -noiopad\n");
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log(" disable I/O buffer insertion (useful for hierarchical or \n");
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@ -131,6 +146,8 @@ struct SynthXilinxPass : public ScriptPass
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bool abc9, dff_mode;
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bool flatten_before_abc;
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int widemux;
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int lut_size;
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int widelut_size;
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void clear_flags() YS_OVERRIDE
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{
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@ -156,6 +173,7 @@ struct SynthXilinxPass : public ScriptPass
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dff_mode = false;
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flatten_before_abc = false;
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widemux = 0;
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lut_size = 6;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -270,9 +288,39 @@ struct SynthXilinxPass : public ScriptPass
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}
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extra_args(args, argidx, design);
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if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc5v" && family != "xc6s")
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if (family == "xcup" || family == "xcu") {
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lut_size = 6;
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widelut_size = 9;
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} else if (family == "xc7" ||
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family == "xc6v" ||
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family == "xc5v" ||
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family == "xc6s") {
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lut_size = 6;
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widelut_size = 8;
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} else if (family == "xc4v" ||
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family == "xc3sda" ||
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family == "xc3sa" ||
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family == "xc3se" ||
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family == "xc3s" ||
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family == "xc2vp" ||
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family == "xc2v") {
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lut_size = 4;
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widelut_size = 8;
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} else if (family == "xcve" || family == "xcv") {
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lut_size = 4;
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widelut_size = 6;
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} else
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log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
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if (widemux != 0 && lut_size != 6)
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log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n");
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if (lut_size != 6) {
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log_warning("Shift register inference not yet supported for family %s.\n", family.c_str());
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nosrl = true;
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nolutram = true;
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}
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if (widemux != 0 && widemux < 2)
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log_cmd_error("-widemux value must be 0 or >= 2.\n");
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@ -292,6 +340,9 @@ struct SynthXilinxPass : public ScriptPass
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void script() YS_OVERRIDE
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{
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std::string lut_size_s = std::to_string(lut_size);
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if (help_mode)
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lut_size_s = "[46]";
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std::string ff_map_file;
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if (help_mode)
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ff_map_file = "+/xilinx/{family}_ff_map.v";
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@ -344,7 +395,7 @@ struct SynthXilinxPass : public ScriptPass
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run("clean", " (skip if '-nosrl' and '-widemux=0')");
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}
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=" + lut_size_s);
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}
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if (check_label("map_dsp", "(skip if '-nodsp')")) {
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@ -353,7 +404,7 @@ struct SynthXilinxPass : public ScriptPass
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// NB: Xilinx multipliers are signed only
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if (help_mode)
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run("techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}");
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else if (family == "xc2v" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
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else if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc3s_mult_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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@ -523,14 +574,12 @@ struct SynthXilinxPass : public ScriptPass
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if (!nosrl || help_mode)
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run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
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std::string techmap_args = " -map +/techmap.v";
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std::string techmap_args = " -map +/techmap.v -D LUT_SIZE=" + lut_size_s;
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if (help_mode)
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techmap_args += " [-map +/xilinx/mux_map.v]";
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else if (widemux > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
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if (help_mode)
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techmap_args += " [-map +/xilinx/arith_map.v]";
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else if (!nocarry) {
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if (!nocarry) {
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techmap_args += " -map +/xilinx/arith_map.v";
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if (vpr)
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techmap_args += " -D _EXPLICIT_CARRY";
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@ -563,6 +612,8 @@ struct SynthXilinxPass : public ScriptPass
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if (help_mode)
|
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run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
|
||||
else if (abc9) {
|
||||
if (lut_size != 6)
|
||||
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
|
||||
if (family != "xc7")
|
||||
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
|
||||
"will use timing for 'xc7' instead.\n", family.c_str());
|
||||
|
|
@ -588,10 +639,19 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
else {
|
||||
std::string abc_opts;
|
||||
if (nowidelut)
|
||||
abc_opts += " -luts 2:2,3,6:5";
|
||||
else
|
||||
abc_opts += " -luts 2:2,3,6:5,10,20";
|
||||
if (lut_size != 6) {
|
||||
if (nowidelut)
|
||||
abc_opts += " -lut " + lut_size_s;
|
||||
else
|
||||
abc_opts += " -lut " + lut_size_s + ":" + std::to_string(widelut_size);
|
||||
} else {
|
||||
if (nowidelut)
|
||||
abc_opts += " -luts 2:2,3,6:5";
|
||||
else if (widelut_size == 8)
|
||||
abc_opts += " -luts 2:2,3,6:5,10,20";
|
||||
else
|
||||
abc_opts += " -luts 2:2,3,6:5,10,20,40";
|
||||
}
|
||||
if (dff_mode)
|
||||
abc_opts += " -dff";
|
||||
if (retime)
|
||||
|
|
@ -607,8 +667,14 @@ struct SynthXilinxPass : public ScriptPass
|
|||
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
|
||||
if (help_mode || !abc9)
|
||||
techmap_args += stringf(" -map %s", ff_map_file.c_str());
|
||||
techmap_args += " -D LUT_WIDTH=" + lut_size_s;
|
||||
run("techmap " + techmap_args);
|
||||
run("xilinx_dffopt");
|
||||
if (help_mode)
|
||||
run("xilinx_dffopt [-lut4]");
|
||||
else if (lut_size == 4)
|
||||
run("xilinx_dffopt -lut4");
|
||||
else
|
||||
run("xilinx_dffopt");
|
||||
run("opt_lut_ins -tech xilinx");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,23 @@
|
|||
read_verilog ../common/add_sub.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
design -save orig
|
||||
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
stat
|
||||
select -assert-count 16 t:LUT2
|
||||
select -assert-count 8 t:LUT2
|
||||
select -assert-count 2 t:CARRY4
|
||||
select -assert-none t:LUT2 t:CARRY4 %% t:* %D
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
stat
|
||||
select -assert-count 8 t:LUT2
|
||||
select -assert-count 6 t:MUXCY
|
||||
select -assert-count 8 t:XORCY
|
||||
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@ hierarchy -top fsm
|
|||
proc
|
||||
flatten
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
|
||||
miter -equiv -make_assert -flatten gold gate miter
|
||||
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
|
||||
|
|
@ -17,3 +19,20 @@ select -assert-count 1 t:LUT2
|
|||
select -assert-count 3 t:LUT5
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
|
||||
miter -equiv -make_assert -flatten gold gate miter
|
||||
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
|
||||
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd fsm # Constrain all select calls below inside the top module
|
||||
stat
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 6 t:FDRE
|
||||
select -assert-count 1 t:LUT1
|
||||
select -assert-count 3 t:LUT3
|
||||
select -assert-count 6 t:LUT4
|
||||
select -assert-count 6 t:MUXF5
|
||||
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
read_verilog ../common/mux.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:LUT3
|
||||
|
||||
select -assert-none t:LUT3 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 4 t:LUT1
|
||||
select -assert-count 2 t:MUXF5
|
||||
select -assert-count 1 t:MUXF6
|
||||
|
||||
select -assert-none t:LUT1 t:MUXF5 t:MUXF6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 4 t:LUT1
|
||||
select -assert-count 3 t:LUT4
|
||||
select -assert-count 2 t:MUXF5
|
||||
select -assert-count 1 t:MUXF6
|
||||
|
||||
select -assert-none t:LUT1 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-max 32 t:LUT*
|
||||
select -assert-max 8 t:MUXF6
|
||||
select -assert-max 4 t:MUXF7
|
||||
|
||||
select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D
|
||||
Loading…
Reference in New Issue