Merge pull request #1670 from rodrigomelo9/master

$readmem[hb] file inclusion is now relative to the Verilog file
This commit is contained in:
Eddie Hung 2020-02-10 08:31:01 -08:00 committed by GitHub
commit d4ff5b2d00
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7 changed files with 152 additions and 3 deletions

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@ -60,6 +60,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "scratchpad" pass
- Added "abc9 -dff"
- Added "synth_xilinx -dff"
- Improved support of $readmem[hb] Memory Content File inclusion
- Added "opt_lut_ins" pass
Yosys 0.8 .. Yosys 0.9

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@ -728,6 +728,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
+cd tests/rpc && bash run-test.sh
+cd tests/memfile && bash run-test.sh
@echo ""
@echo " Passed \"make test\"."
@echo ""

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@ -2903,9 +2903,19 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
std::ifstream f;
f.open(mem_filename.c_str());
yosys_input_files.insert(mem_filename);
if (f.fail())
if (f.fail()) {
#ifdef _WIN32
char slash = '\\';
#else
char slash = '/';
#endif
std::string path = filename.substr(0, filename.find_last_of(slash)+1);
f.open(path + mem_filename.c_str());
yosys_input_files.insert(path + mem_filename);
} else {
yosys_input_files.insert(mem_filename);
}
if (f.fail() || GetSize(mem_filename) == 0)
log_file_error(filename, linenum, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);

1
tests/memfile/.gitignore vendored Normal file
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@ -0,0 +1 @@
temp*

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@ -0,0 +1,64 @@
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000
00001111000000001111111100000000

23
tests/memfile/memory.v Normal file
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@ -0,0 +1,23 @@
// A memory initialized with an external file
module memory (
input clk_i,
input we_i,
input [5:0] addr_i,
input [31:0] data_i,
output reg [31:0] data_o
);
parameter MEMFILE = "";
reg [31:0] mem [0:63];
initial $readmemb(MEMFILE,mem);
always @(posedge clk_i) begin
if (we_i)
mem[addr_i] <= data_i;
data_o <= mem[addr_i];
end
endmodule

49
tests/memfile/run-test.sh Executable file
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@ -0,0 +1,49 @@
#!/bin/bash
set -e
mkdir -p temp
cp content1.dat temp/content2.dat
cd ..
echo "Running from the parent directory with content1.dat"
../yosys -qp "read_verilog -defer memfile/memory.v; chparam -set MEMFILE \"content1.dat\" memory"
echo "Running from the parent directory with temp/content2.dat"
../yosys -qp "read_verilog -defer memfile/memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory"
echo "Running from the parent directory with memfile/temp/content2.dat"
../yosys -qp "read_verilog -defer memfile/memory.v; chparam -set MEMFILE \"memfile/temp/content2.dat\" memory"
cd memfile
echo "Running from the same directory with content1.dat"
../../yosys -qp "read_verilog -defer memory.v; chparam -set MEMFILE \"content1.dat\" memory"
echo "Running from the same directory with temp/content2.dat"
../../yosys -qp "read_verilog -defer memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory"
cd temp
echo "Running from a child directory with content1.dat"
../../../yosys -qp "read_verilog -defer ../memory.v; chparam -set MEMFILE \"content1.dat\" memory"
echo "Running from a child directory with temp/content2.dat"
../../../yosys -qp "read_verilog -defer ../memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory"
echo "Running from a child directory with content2.dat"
../../../yosys -qp "read_verilog -defer ../memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory"
cd ..
echo "Checking a failure when zero length filename is provided"
if ../../yosys -qp "read_verilog memory.v"; then
echo "The execution should fail but it didn't happen, which is WRONG."
exit 1
else
echo "Execution failed, which is OK."
fi
echo "Checking a failure when not existing filename is provided"
if ../../yosys -qp "read_verilog -defer memory.v; chparam -set MEMFILE \"content3.dat\" memory"; then
echo "The execution should fail but it didn't happen, which is WRONG."
exit 1
else
echo "Execution failed, which is OK."
fi