Split latch check

tests/efinix/latches.v

@@ -22,37 +22,3 @@ module latchsr
 		else if ( en )
 			q <= d;
 endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule

tests/efinix/latches.ys

@@ -2,19 +2,32 @@ read_verilog latches.v
 design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
-flatten
+hierarchy -top latchp
+# Can't run any sort of equivalence check because latches are blown to LUTs
 synth_efinix
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
 
 design -load read
-
+proc
+hierarchy -top latchn
+# Can't run any sort of equivalence check because latches are blown to LUTs
 synth_efinix
-flatten
-cd top
-#Internall cell type $_DLATCH_P_. Should be realized by using LUTs.
-#The same result by using just synth_efinix.
-select -assert-count 3  t:$_DLATCH_P_
-select -assert-count 3  t:EFX_LUT4
-select -assert-none t:$_DLATCH_P_ t:EFX_LUT4 %% t:* %D
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchsr
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D