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Even more obvious testcase

This commit is contained in:
Eddie Hung 2019-12-11 23:52:05 -08:00
parent 61a1f3f49b
commit 4a80510877
1 changed files with 5 additions and 6 deletions
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11
tests/sat/initval.ys
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@ -5,12 +5,11 @@ sat -seq 10 -prove-asserts
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
(* init = 1'b0 *)
wire o;
(* init = 1'bx *)
wire p = o;
$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
module top(input clk, i, output [1:0] o);
(* init = 2'bx0 *)
wire [1:0] o;
assign o[1] = o[0];
$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0]));
endmodule
EOT
sat -seq 1