split rest od ff's

This commit is contained in:
Miodrag Milanovic 2019-10-04 12:51:45 +02:00
parent 3de7889d08
commit 2c3e140246
3 changed files with 18 additions and 31 deletions

View File

@ -43,9 +43,6 @@ hierarchy -top ndffnr
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4

View File

@ -13,25 +13,3 @@ module dffe
if ( en )
q <= d;
endmodule
module top (
input clk,
input en,
input a,
output b,b1,
);
dff u_dff (
.clk (clk ),
.d (a ),
.q (b )
);
dffe u_ndffe (
.clk (clk ),
.en (en),
.d (a ),
.q (b1 )
);
endmodule

View File

@ -1,12 +1,24 @@
read_verilog dffs.v
hierarchy -top top
design -save read
proc
flatten
hierarchy -top dff
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
proc
hierarchy -top dffe
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 2 t:EFX_FF
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D