Added a test case

2020-01-01 16:24:30 +01:00 · 2020-01-01 16:24:30 +01:00 · a1344ec06e
parent e0c879684f
commit a1344ec06e
1 changed files with 19 additions and 0 deletions
--- a/tests/arch/xilinx/bug1605.ys
+++ b/tests/arch/xilinx/bug1605.ys
@ -0,0 +1,19 @@
+read_verilog <<EOT
+module top(inout io);
+    wire in;
+    wire t;
+    wire o;
+
+    IOBUF IOBUF(
+      .I(in),
+      .T(t),
+      .IO(io),
+      .O(o)
+    );
+endmodule
+EOT
+
+synth_xilinx
+cd top
+select -assert-count 1 t:IOBUF
+select -assert-none t:* t:IOBUF %d