mirror of https://github.com/YosysHQ/yosys.git
Refactor +/cmp2lcu.v into recursive techmap
This commit is contained in:
Eddie Hung
parent
8e851badc4
commit
f68d723cdc
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@ -29,52 +29,79 @@ generate
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// Transform $le into $ge by swapping A and B
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$ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
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end
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else if (A_WIDTH != B_WIDTH) begin
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else begin
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// Perform sign extension on A and B
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
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wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
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if (_TECHMAP_CELLTYPE_ == "$gt")
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$gt #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(WIDTH), .B_WIDTH(WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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else if (_TECHMAP_CELLTYPE_ == "$ge")
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$ge #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(WIDTH), .B_WIDTH(WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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else
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wire _TECHMAP_FAIL_ = 1;
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end
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else begin
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localparam cmp_width = `LUT_WIDTH/2;
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localparam lcu_width = (A_WIDTH+cmp_width-1)/cmp_width;
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wire [lcu_width-1:0] P, G, CO;
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genvar i, j;
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for (i = 0; i < A_WIDTH; i=i+cmp_width) begin
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wire [cmp_width-1:0] PP, GG;
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for (j = cmp_width-1; j >= 0 && i+j < A_WIDTH; j = j-1) begin
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// Bit-wise equality (xnor) of sign-extended A and B
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assign PP[j] = A[i+j] ^~ B[i+j];
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if (i+j == A_WIDTH-1 && A_SIGNED && B_SIGNED)
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assign GG[j] = ~A[i+j] & B[i+j];
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else if (j == cmp_width-1)
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assign GG[j] = A[i+j] & ~B[i+j];
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else
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// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
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// from MSB down, deferring to less significant bits if the
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// MSBs are equal
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assign GG[j] = &PP[cmp_width-1:j+1] & (A[i+j] & ~B[i+j]);
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end
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// Propagate only if all bit pairs are equal
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// (inconclusive evidence to say A >= B)
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assign P[i/cmp_width] = &PP;
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// Generate if any bit pairs call for it
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assign G[i/cmp_width] = |GG;
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end
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// For $ge operation, start with the assumption that A and B are
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// equal (propagating this equality if A and B turn out to be so)
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if (_TECHMAP_CELLTYPE_ == "$ge")
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wire CI = 1'b1;
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localparam CI = 1'b1;
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else
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wire CI = 1'b0;
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$lcu #(.WIDTH(lcu_width)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
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assign Y = CO[lcu_width-1];
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localparam CI = 1'b0;
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$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(0), .BUDGET(`LUT_WIDTH), .CI(CI))
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_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(), .G(), .PP(1'b1), .GG(1'b0), .Y(Y));
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end
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endgenerate
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endmodule
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module $__CMP2LCU (A, B, P, G, PP, GG, Y);
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parameter AB_WIDTH = 0;
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parameter AB_SIGNED = 0;
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parameter LCU_WIDTH = 0;
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parameter BUDGET = 0;
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parameter CI = 0;
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input [AB_WIDTH-1:0] A;
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input [AB_WIDTH-1:0] B;
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input [LCU_WIDTH-1:0] P;
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input [LCU_WIDTH-1:0] G;
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input PP;
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input GG;
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output Y;
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parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
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parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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generate
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if (AB_WIDTH == 0) begin
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if (BUDGET < `LUT_WIDTH)
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
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_TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, PP}), .G({G, GG}), .PP(1'b1), .GG(1'b0), .Y(Y));
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else begin
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wire [LCU_WIDTH-1:0] CO;
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$lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
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assign Y = CO[LCU_WIDTH-1];
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end
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end
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else begin
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if (BUDGET < 2)
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
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_TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, PP}), .G({G, GG}), .PP(1'b1), .GG(1'b0), .Y(Y));
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else begin
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wire PPP, GGG;
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// Bit-wise equality (xnor) of A and B
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assign PPP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];
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if (AB_SIGNED)
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assign GGG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];
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else if (BUDGET == `LUT_WIDTH)
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assign GGG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];
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else
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// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
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// from MSB down, deferring to less significant bits if the
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// MSBs are equal
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assign GGG = PP & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-2), .CI(CI))
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_TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P), .G(G),
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// Propagate only if all bit pairs are equal
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// (inconclusive evidence to say A >= B)
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.PP(PP & PPP),
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// Generate if any bit pairs call for it
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.GG(GG | GGG),
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.Y(Y));
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end
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end
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endgenerate
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endmodule
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@ -1,5 +1,5 @@
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read_verilog <<EOT
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module top(input [11:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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assign gtu = a > b;
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assign gts = $signed(a) > $signed(b);
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assign ltu = a < b;
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