mirror of https://github.com/YosysHQ/yosys.git
25 lines
680 B
Plaintext
25 lines
680 B
Plaintext
read_verilog <<EOT
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module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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assign gtu = a > b;
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assign gts = $signed(a) > $signed(b);
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assign ltu = a < b;
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assign lts = $signed(a) < $signed(b);
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assign geu = a >= b;
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assign ges = $signed(a) >= $signed(b);
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assign leu = a <= b;
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assign les = $signed(a) <= $signed(b);
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endmodule
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EOT
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proc
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
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design -load postopt
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select -assert-count 8 t:$lcu
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -load preopt
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
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design -load postopt
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select -assert-count 8 t:$lcu
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select -assert-none t:$gt t:$ge t:$lt t:$le
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