mirror of https://github.com/YosysHQ/yosys.git
opt_expr: add failing $xnor test
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@ -14,7 +14,7 @@ equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$xor
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select -assert-none t:$xnor
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select -assert-count 2 t:$_NOT_
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select -assert-count 2 t:$not
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design -load read
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@ -38,3 +38,15 @@ equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
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select -assert-count 1 t:$_NOT_
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design -reset
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read_verilog <<EOT
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module top(input a, output [1:0] w, x, y, z);
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assign w = a^1'b0;
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assign x = a^1'b1;
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assign y = a~^1'b0;
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assign z = a~^1'b1;
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endmodule
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EOT
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equiv_opt opt_expr
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