mirror of https://github.com/YosysHQ/yosys.git
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
This commit is contained in:
whitequark
parent
3f4460a186
commit
081d9318bc
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@ -37,7 +37,17 @@ bram $__ECP5_DP16KD
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clkpol 2 3
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endbram
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# The syn_* attributes are described in:
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# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
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attr_icase 1
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match $__ECP5_PDPW16KD
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 2048
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min efficiency 5
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shuffle_enable A
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@ -45,8 +55,60 @@ match $__ECP5_PDPW16KD
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or_next_if_better
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endmatch
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match $__ECP5_PDPW16KD
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__ECP5_PDPW16KD
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__ECP5_DP16KD
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 2048
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min efficiency 5
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shuffle_enable A
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or_next_if_better
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endmatch
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match $__ECP5_DP16KD
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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or_next_if_better
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endmatch
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match $__ECP5_DP16KD
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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endmatch
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@ -11,7 +11,16 @@ bram $__TRELLIS_DPR16X4
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clkpol 0 2
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endbram
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# The syn_* attributes are described in:
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# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
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attr_icase 1
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match $__TRELLIS_DPR16X4
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attribute !syn_ramstyle syn_ramstyle=auto syn_ramstyle=distributed
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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make_outreg
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min wports 1
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endmatch
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@ -10,16 +10,16 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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integer i,j = 16'hACE1;
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integer i,j = 64'hF4B1CA8127865242;
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initial
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for (i = 0; i <= DEPTH; i++) begin
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// In case this ROM will be implemented in fabric: fill the memory with some data
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// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
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// emit any LUTs at all for `memory[i] = i;`, just a latch.
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memory[i] = j;
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j = j ^ (j >> 7);
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j = j ^ (j << 9);
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j = j ^ (j >> 13);
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memory[i] = j * 64'h2545F4914F6CDD1D;
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j = j ^ (j >> 12);
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j = j ^ (j << 25);
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j = j ^ (j >> 27);
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end
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always @(posedge clk) begin
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@ -0,0 +1,284 @@
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# ================================ RAM ================================
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# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # too inefficient
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select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD # any case works
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM
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select -assert-count 180 t:TRELLIS_FF
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# RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # too inefficient
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select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested BROM but this is a RAM
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested BROM but this is a RAM
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select -assert-count 90 t:TRELLIS_FF
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# RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "distributed" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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# ================================ ROM ================================
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# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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write_ilang
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # too inefficient
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM
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select -assert-min 18 t:LUT4
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# ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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write_ilang
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # too inefficient
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select -assert-min 9 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
|
||||
select -assert-min 9 t:LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
|
||||
select -assert-min 9 t:LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set syn_ramstyle "block_ram" m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM
|
||||
select -assert-min 9 t:LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM
|
||||
select -assert-min 9 t:LUT4
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
# ================================ RAM ================================
|
||||
# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
|
|
@ -46,6 +47,13 @@ setattr -set ram_block 1 m:memory
|
|||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set syn_ramstyle "registers" m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
|
||||
select -assert-min 1 t:SB_DFFE
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set logic_block 1 m:memory
|
||||
|
|
@ -67,6 +75,7 @@ synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
|||
select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM
|
||||
select -assert-min 1 t:SB_DFFE
|
||||
|
||||
# ================================ ROM ================================
|
||||
# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
|
|
@ -110,6 +119,13 @@ setattr -set rom_block 1 m:memory
|
|||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set syn_romstyle "logic" m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
|
||||
select -assert-min 1 t:SB_LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set logic_block 1 m:memory
|
||||
|
|
|
|||
Loading…
Reference in New Issue