Add testcase

This commit is contained in:
Eddie Hung 2019-11-22 16:41:05 -08:00
parent c03b6a3e9c
commit 2ef2e2c040
1 changed files with 26 additions and 0 deletions

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tests/various/submod.ys Normal file
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read_verilog <<EOT
module top(input a, output [1:0] b);
wire c;
(* submod="bar" *) sub s1(a, c);
assign b[0] = c;
endmodule
module sub(input a, output c);
assign c = a;
endmodule
EOT
hierarchy -top top
proc
design -save gold
submod
flatten
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter