Eddie Hung
48aec34e0d
abc_box_id -> abc9_box_id in test
2020-01-23 18:53:14 -08:00
Eddie Hung
5aaa19f1ab
Update tests with reduced area
2020-01-21 16:50:04 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
cd8f55a911
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
...
Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
5507c328ff
Add #1644 testcase
2020-01-17 15:57:52 -08:00
Eddie Hung
ad6c49fff1
ice40_dsp: add test
2020-01-17 15:38:26 -08:00
Jeff Wang
8ef5c7d48c
scoped enum tests
2020-01-16 18:13:30 -05:00
Jeff Wang
caf35896da
enum in package test
2020-01-16 18:09:03 -05:00
Jeff Wang
febe7706a2
simple enum test
2020-01-16 18:09:03 -05:00
Eddie Hung
2245afa142
More rigorous test
2020-01-16 09:15:42 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5918ede9bd
abc9: aAdd test to check $_NOT_s are absorbed
2020-01-15 14:36:05 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
...
autoname: do not rename ports
2020-01-14 11:40:54 -08:00
Eddie Hung
9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630
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read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-14 11:40:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
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Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
00964e999d
autoname: add testcase with $-prefix-ed port
2020-01-14 10:13:03 -08:00
Eddie Hung
565d349dc9
Add #1630 testcase
2020-01-13 21:27:53 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
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abc9: add some scripts/options into "scratchpad"
2020-01-13 09:04:20 -08:00
Eddie Hung
ae619ba87a
Add #1626 testcase
2020-01-12 15:21:26 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Miodrag Milanovic
ccfe1e5909
this one is fine
2020-01-10 15:20:50 +01:00
Miodrag Milanovic
af852a0ea8
Fix tests
2020-01-10 14:48:01 +01:00
Eddie Hung
a10016ccc5
Add abc9 sanity test
2020-01-09 18:17:06 -08:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
0d3f10d3cc
Add testcases
2020-01-07 11:44:20 -08:00
Eddie Hung
7c878bf397
tests/aiger: write Yosys output
2020-01-07 11:44:03 -08:00
Eddie Hung
3df869cc7c
Add testcase from #1459
2020-01-06 16:22:22 -08:00
Eddie Hung
6e866030c2
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests
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Fix a few issues in tests/arch/*
2020-01-01 13:31:46 -08:00
Eddie Hung
52fe1e0c44
Revert insertion of 'reg', leave note behind
2020-01-01 09:05:46 -08:00
Miodrag Milanovic
a1344ec06e
Added a test case
2020-01-01 16:24:30 +01:00
Eddie Hung
713484fa66
Do not do call equiv_opt when no sim model exists
2019-12-31 18:40:30 -08:00
Eddie Hung
a59016b146
Fix warnings
2019-12-31 18:40:11 -08:00
Eddie Hung
c082329af3
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
Eddie Hung
ccc0a740d2
Add some abc9 dff tests
2019-12-31 16:16:05 -08:00
Eddie Hung
0c4be94a02
Add -D DFF_MODE to abc9_map test
2019-12-30 20:13:25 -08:00
Eddie Hung
fc4b8b8991
Remove submod changes
2019-12-30 14:56:14 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default
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Make iopad option default for all xilinx flows
2019-12-30 20:34:31 +01:00
Eddie Hung
c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588
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Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
2019-12-30 10:01:02 -08:00
Miodrag Milanovic
f9749c202c
Fix new tests
2019-12-28 16:43:19 +01:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Miodrag Milanovic
a82c701668
Make test without iopads
2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a
Revert "Fix xilinx tests, when iopads are default"
...
This reverts commit 477e43d921
.
2019-12-28 16:12:45 +01:00
Eddie Hung
011f749ecf
Update resource count
2019-12-28 02:15:11 -08:00
Eddie Hung
d45869855c
Add #1598 testcase
2019-12-27 16:44:57 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
477e43d921
Fix xilinx tests, when iopads are default
2019-12-21 13:18:44 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570
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mem_arst.v: do not redeclare ANSI port
2019-12-19 12:21:22 -05:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
f382164d6e
tests/xilinx: fix flaky mux test
2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
...
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
Eddie Hung
aed67dd020
abc9 needs a clean afterwards
2019-12-16 18:42:23 -08:00
Eddie Hung
378d9e6e0c
Add another test
2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f
Accidentally commented out tests
2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5
Merge blockram tests
2019-12-16 13:01:51 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
f3f59910eb
Removing fixed attribute value to !ramstyle rules
2019-12-15 23:51:58 -06:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
Eddie Hung
d86d073ad6
Add testcase
2019-12-13 10:26:30 -08:00
Diego H
1c96345587
Renaming BRAM memory tests for the sake of uniformity
2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f
Remove extraneous synth_xilinx call
2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a
Add tests for these new models
2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df
Add #1460 testcase
2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6
Add test
2019-12-12 14:43:13 -08:00
Diego H
e33f407655
Adding a note (TODO) in the memory_params.ys check file
2019-12-12 16:06:46 -06:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Eddie Hung
23fcfd0adb
Make SV2017 compliant courtesy of @wsnyder
2019-12-12 07:34:07 -08:00
Eddie Hung
4a80510877
Even more obvious testcase
2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b
Make testcase clearer with \o having its own init
2019-12-11 23:48:09 -08:00
Eddie Hung
151f7533e8
Add testcase
2019-12-11 16:52:37 -08:00
Eddie Hung
e75ca29b19
Add test: 'Warning: ignoring initial value on non-register: \o'
2019-12-11 11:26:54 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33
unmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 14:20:35 -08:00
Eddie Hung
705e520a52
Add a quick testcase for unknown modules as inout
2019-12-09 13:14:46 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f
Fix for non-deterministic test
2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a
tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43
Check SB_CARRY name also preserved
2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4
Add testcase
2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
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Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5
update test
2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
c61186dd9d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 13:24:03 -08:00
Eddie Hung
ff1e357682
Add multiple driver testcase
2019-11-27 13:22:26 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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opt_share: Fix handling of fine cells.
2019-11-27 11:23:16 +01:00
Eddie Hung
f6c0ec1d09
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
2019-11-27 01:03:33 -08:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
...
This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
6318e3ce6d
Fix wire width
2019-11-26 23:38:49 -08:00
Eddie Hung
de3476cc23
No need for -abc9
2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
...
Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
4a0198128e
Add citation
2019-11-26 22:51:16 -08:00
Eddie Hung
15042eaf57
Remove notes
2019-11-26 22:41:35 -08:00
Eddie Hung
222e199b73
Add testcase derived from fastfir_dynamictaps benchmark
2019-11-26 21:26:30 -08:00
Eddie Hung
dd317c9280
Add testcase where \init is copied
2019-11-25 16:07:35 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910
attempt to fix formatting
2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a
gowin: add and test dff init values
2019-11-25 14:33:21 +01:00
Eddie Hung
b46e636c91
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
2019-11-23 08:38:48 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
5cd3d3db0a
Remove redundant flatten
2019-11-22 22:28:10 -08:00
Eddie Hung
08f85e6438
Stray dump
2019-11-22 20:53:48 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
4fdcf8f7d7
Add another test with constant driver
2019-11-22 17:23:34 -08:00
Eddie Hung
74ea438136
Add testcase for signal used as part input part output
2019-11-22 16:52:55 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
8779faf789
Cleanup spacing
2019-11-22 16:50:09 -08:00
Eddie Hung
2ef2e2c040
Add testcase
2019-11-22 16:48:11 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
c761fa49b7
Missing endmodule
2019-11-22 12:37:57 -08:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always
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sv: Error checking for always_comb, always_latch and always_ff
2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48
gowin: Remove show command from tests.
2019-11-22 14:49:35 +01:00
Eddie Hung
6841e3b1c2
Another sloppy mistake!
2019-11-21 16:33:20 -08:00
Eddie Hung
fe36275234
Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
2019-11-21 16:32:52 -08:00
Eddie Hung
39fdcb892b
async2sync -> clk2fflogic
2019-11-21 16:27:34 -08:00
Eddie Hung
5a30e3ac3b
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 16:15:25 -08:00
Eddie Hung
911a152b39
Add test
2019-11-21 16:13:28 -08:00
David Shah
49b670ca38
sv: Add tests for SV always types
...
Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 21:06:28 +00:00
Eddie Hung
cd9e830b67
Add multi clock test
2019-11-20 13:28:55 -08:00
Eddie Hung
1cc106452f
Add a equiv test too
2019-11-19 17:05:14 -08:00
Eddie Hung
90c5ca330c
Add two tests
2019-11-19 16:57:58 -08:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin
...
Improvements for gowin support
2019-11-19 17:29:27 +01:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Pepijn de Vos
32f0296df1
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030
fix fsm test with proper clock enable polarity
2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7
Fixed tests
2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc
fix wide luts
2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df
don't cound exact luts in big muxes; futile and fragile
2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391
add tristate buffer and test
2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224
do not use wide luts in testcase
2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b
ALU sim tweaks
2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964
Add some tests
...
Copied from Efinix.
* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a
fixed error
2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8
Unify verilog style
2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2
Common memory test now shared
2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9
Remove not needed tests
2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c
Share common tests
2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf
fix yosys path
2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675
Fix path to yosys
2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1
Add async2sync
2019-10-18 11:00:27 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix
2019-10-18 10:54:28 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic
2019-10-18 10:53:56 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352
2019-10-18 10:52:50 +02:00
Miodrag Milanovic
b659082e4a
hierarchy - proc reorder
2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7
hierarchy - proc reorder
2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9
hierarchy - proc reorder
2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20
hierarchy - proc reorder
2019-10-18 08:06:57 +02:00
Miodrag Milanovic
980df499ab
Make equivalence work with latest master
2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f
split muxes synth per type
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801
Test dffs separetely
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124
Split latches into separete tests
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718
Fix formatting
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90
Clean verilog code from not used define block
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5
Removed alu and div_mod test as agreed, ignore generated files
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe
Test per flip-flop type
2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320
Add -assert
2019-10-17 17:10:42 +02:00
Eddie Hung
8422ad3e3a
Use built-in async2sync call as per #1417
2019-10-17 17:10:42 +02:00
Eddie Hung
5b7bc3ab85
Update mul test to DSP48E1
2019-10-17 17:10:02 +02:00
Eddie Hung
08bd1816e3
Update area for div_mod
2019-10-17 17:10:02 +02:00
Eddie Hung
a12801843b
Add comment for lack of tristate logic pointing to #1225
2019-10-17 17:10:02 +02:00
Eddie Hung
eded90b6b4
Move $x to end as 7f0eec8
2019-10-17 17:10:02 +02:00
SergeyDegtyar
305672170b
adffs test update (equiv_opt -multiclock)
2019-10-17 17:10:02 +02:00
Sergey
bb70eb977d
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
68f9239c57
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df6d0b95da
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
c340d54657
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
205f52ffe5
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df7fe40529
Fix div_mod test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
7bc8f0c2e2
Add comment with expected behavior for latches,tribuf tests;Update adffs test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
489444bcba
Fix latches.ys test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
6331fa5b02
Remove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 17:10:02 +02:00
SergeyDegtyar
757c476f62
Add smoke tests to tests/xilinx
2019-10-17 17:10:02 +02:00
SergeyDegtyar
ca7a58bcc8
Add comments for unproven cells.
2019-10-17 17:08:38 +02:00
SergeyDegtyar
2ae7dec530
Add tests for Xilinx UG901 examples
2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
Eddie Hung
3fb604c75d
Revert "Add test that is expecting to fail"
...
This reverts commit c28d4b8047
.
2019-10-08 12:41:26 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Miodrag Milanovic
c0fa6f3e1a
Split mux tests per type
2019-10-04 13:05:16 +02:00
Miodrag Milanovic
1b80489486
Split latch check
2019-10-04 13:00:09 +02:00
Miodrag Milanovic
2c3e140246
split rest od ff's
2019-10-04 12:51:45 +02:00
Miodrag Milanovic
3de7889d08
Separate check for ff's types
2019-10-04 12:48:27 +02:00
Miodrag Milanovic
286a272872
Cleaned tests
2019-10-04 12:42:06 +02:00
Miodrag Milanovic
f94dc2c072
Remove not needed tests
2019-10-04 12:41:41 +02:00
Miodrag Milanovic
ef417fb1b3
Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix
2019-10-04 12:20:49 +02:00
Miodrag Milanovic
03a3deec43
Cleanup and formating
2019-10-04 11:09:59 +02:00
Miodrag Milanovic
a5844e3ceb
split latches into separate checks
2019-10-04 11:08:42 +02:00
Miodrag Milanovic
3238ee7d35
check muxes per type
2019-10-04 11:04:18 +02:00
Miodrag Milanovic
91ad3ab717
check ff's separately
2019-10-04 11:00:49 +02:00
Miodrag Milanovic
3d3479b0af
Cleanup top modules and not used defines
2019-10-04 10:57:47 +02:00
Miodrag Milanovic
1435b9bf97
remove alu test
2019-10-04 10:55:13 +02:00
Miodrag Milanovic
b932654964
Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic
2019-10-04 10:52:16 +02:00
Miodrag Milanovic
7785f23719
Check latches type one by one
2019-10-04 10:31:51 +02:00
Miodrag Milanovic
3358b2f185
Removed top module where not needed
2019-10-04 09:53:54 +02:00
Miodrag Milanovic
3c40c81030
Test muxes synth one by one
2019-10-04 08:52:54 +02:00
Miodrag Milanovic
d6ef9b1a6b
Cleaned verilog code from not used defines
2019-10-04 08:45:58 +02:00
Miodrag Milanovic
abb5a3a44d
Check for MULT18X18D, since that is working now
2019-10-04 08:44:10 +02:00
Miodrag Milanovic
9e8175fc75
Check flops one by one
2019-10-04 08:42:29 +02:00
Miodrag Milanovic
d19f765a58
Removed alu and div_mod tests as agreed
2019-10-04 08:41:53 +02:00
Eddie Hung
045f344038
Use `sat -tempinduct` and comments for why equiv_opt not sufficient
2019-10-03 11:11:50 -07:00
Eddie Hung
bd5889640b
Disable equiv check for ice40 latches
2019-10-03 10:45:53 -07:00
Eddie Hung
5d680590d6
Use equiv_opt -async2sync for xilinx
2019-10-03 10:30:33 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
David Shah
9b9d24f15b
sv: Improve tests
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
abc155715d
sv: Add test scripts for typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
af25585170
sv: Add support for memories of a typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
30d2326030
sv: Add support for memory typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60
sv: Fix typedefs in packages
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
c962951612
sv: Fix typedef parameters
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
e4bd5aaebf
Fix test
2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda
Update test
2019-10-02 18:03:45 -07:00
Eddie Hung
e730a595ee
Add test
2019-10-02 18:01:41 -07:00
Eddie Hung
c28d4b8047
Add test that is expecting to fail
2019-10-02 14:52:40 -07:00
Eddie Hung
a4f2f7d23c
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
Sergey
eb750670e3
run-test.sh Move $x at end of line.
2019-10-01 11:14:12 +03:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix
2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic
2019-10-01 10:57:09 +03:00
Sergey
fc56459746
run-test.sh Move $x at end of line.
2019-10-01 10:55:34 +03:00
Eddie Hung
1caaf51492
equiv_opt with -assert
2019-09-30 19:54:59 -07:00
Eddie Hung
f8d5e11aa7
Update resource count for alu.ys
2019-09-30 19:54:04 -07:00
Eddie Hung
369652d4b9
Add test
2019-09-30 17:20:39 -07:00
Eddie Hung
8b239ee707
Add quick test
2019-09-30 15:34:04 -07:00
Eddie Hung
d992858318
Move $x to end as per 7f0eec8
2019-09-30 15:15:14 -07:00
Eddie Hung
eeb86247c5
Update fsm.ys resource count
2019-09-30 15:14:41 -07:00
Eddie Hung
0bbd1b6364
Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352
2019-09-30 14:57:55 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc
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rpc: new frontend
2019-09-30 17:38:20 +00:00
whitequark
99a7f39084
rpc: new frontend.
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A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
Eddie Hung
6216e45eda
Add latch test modified from #1363
2019-09-30 12:52:43 +02:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Miodrag Milanovic
7f0eec8270
Change order of parameters, to work on other os
2019-09-27 11:31:55 +02:00
Eddie Hung
a009314597
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
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ICE40 tests. adffs test update (equiv_opt -multiclock).
2019-09-25 16:43:24 -07:00
SergeyDegtyar
b66364ada2
Change sync controls to async.
2019-09-25 14:43:26 +03:00
SergeyDegtyar
fc6ebf8268
adffs test update (equiv_opt -multiclock).
2019-09-24 14:55:32 +03:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
SergeyDegtyar
1070f2e90b
Add new tests for Efinix architecture.
...
Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
2019-09-23 15:51:41 +03:00
SergeyDegtyar
27377c4663
Add new tests for Anlogic architecture
...
Problems/questions:
- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
- Internal cell type $_TBUF_ is present.
2019-09-23 12:12:02 +03:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Eddie Hung
4100825b81
Add more complicated macc testcase
2019-09-19 22:39:15 -07:00
Eddie Hung
2f98f9deee
Add mac.sh and macc_tb.v for testing
2019-09-19 18:08:16 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
65fa8adf6c
Format macc.v
2019-09-19 11:02:14 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
c663a3680b
Remove stat
2019-09-18 12:44:34 -07:00
Eddie Hung
f7dbfef792
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:40:21 -07:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Eddie Hung
c9fe4d7992
Add .gitignore
2019-09-18 12:11:33 -07:00
Eddie Hung
c3cba7ab93
Refine macc testcase
2019-09-18 12:07:25 -07:00
SergeyDegtyar
5eb91fa69f
Add comment to dpram test about related issue.
2019-09-18 12:16:04 +03:00
SergeyDegtyar
c597c2f2ae
adffs test update (equiv_opt -multiclock). div_mod test fix
2019-09-17 12:19:31 +03:00
Eddie Hung
f492567c87
Oops
2019-09-13 18:19:07 -07:00
Eddie Hung
a2eee9ebef
Add counter-example from @cliffordwolf
2019-09-13 16:41:10 -07:00
Eddie Hung
14d72c39c3
Revert "Make one check $shift(x)? only; change testcase to be 8b"
...
This reverts commit e2c2d784c8
.
2019-09-13 16:33:18 -07:00
Eddie Hung
a1123b095c
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-12 12:11:11 -07:00
David Shah
6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
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Add equiv_opt -multiclock
2019-09-12 12:26:28 +01:00
Eddie Hung
7d644f40ed
Add AREG=2 BREG=2 test
2019-09-11 17:05:47 -07:00
Eddie Hung
c0f26c2da8
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 13:37:11 -07:00
Eddie Hung
bdb5e0f29c
Cope with presence of reset muxes too
2019-09-11 13:36:37 -07:00
Eddie Hung
f46ef47893
Add more tests
2019-09-11 13:22:41 -07:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Eddie Hung
6a95ecd41d
Update test with a/b reset
2019-09-11 10:13:13 -07:00
Eddie Hung
36d6db7f8a
Extend test for RSTP and RSTM
2019-09-11 09:09:08 -07:00
David Shah
c43e52d2d7
Add equiv_opt -multiclock
...
Signed-off-by: David Shah <dave@ds0.me>
2019-09-11 13:55:59 +01:00
Eddie Hung
fc7008671f
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:57:25 -07:00
Eddie Hung
3a8582081e
proc instead of prep
2019-09-11 00:14:06 -07:00
Eddie Hung
6b23c7c227
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:07:33 -07:00
Eddie Hung
580faae8ad
Add unsigned case
2019-09-11 00:07:17 -07:00
Eddie Hung
feb3fa65a3
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-11 00:01:31 -07:00
Eddie Hung
1fc50a03fc
Add SIMD test
2019-09-09 21:40:06 -07:00
Sean Cross
702ce405c1
tests: ice40: fix div_mod SB_LUT4 count
...
This test is failing due to one of the changes present in this patchset.
Adjust the test to match the newly-observed values.
https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-10 08:47:16 +08:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Eddie Hung
e68507a716
Update macc test
2019-09-06 23:19:03 -07:00
Eddie Hung
de8adecd39
Merge branch 'master' of github.com:YosysHQ/yosys
2019-09-06 22:52:00 -07:00
Eddie Hung
173c7936c3
Add missing -assert to equiv_opt
2019-09-06 22:51:44 -07:00
Eddie Hung
97e1520b13
Missing equiv_opt -assert
2019-09-06 22:50:03 -07:00
Eddie Hung
e2c2d784c8
Make one check $shift(x)? only; change testcase to be 8b
2019-09-06 22:48:23 -07:00
Eddie Hung
51b559af2c
Usee equiv_opt -assert
2019-09-06 22:48:04 -07:00
Eddie Hung
38e73a3788
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-05 13:01:34 -07:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
Eddie Hung
ef0681ea4c
simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select
2019-09-05 08:43:22 -07:00
Eddie Hung
11f623cbe0
Revert "abc9 followed by clean otherwise netlist could be invalid for sim"
...
This reverts commit 6fe1ca633d
.
2019-09-05 08:25:09 -07:00
Eddie Hung
ba629e6a28
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-04 15:36:07 -07:00
Eddie Hung
6fe1ca633d
abc9 followed by clean otherwise netlist could be invalid for sim
2019-09-04 15:20:04 -07:00
Eddie Hung
229e54568e
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-04 12:37:48 -07:00
Eddie Hung
3732d421c5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-04 12:37:42 -07:00
Eddie Hung
0cee66e759
Add peepopt_dffmuxext tests
2019-09-04 12:34:44 -07:00
SergeyDegtyar
93f305b1c5
Remove stat command form shifter.ys test
2019-09-04 14:57:45 +03:00
SergeyDegtyar
a203c8569c
Fix ecp5 tests
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- remove *_synth.v files and generation in scripts;
- change synth_ice40 to synth_ecp5;
2019-09-04 12:15:52 +03:00
Eddie Hung
0ca0706630
Expand test with `hierarchy' without -auto-top
2019-09-03 12:17:26 -07:00
Eddie Hung
8124716830
Add `read -noverific` before read
2019-09-03 10:52:34 -07:00
Eddie Hung
d6a84a78a7
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
2019-09-03 10:49:21 -07:00
SergeyDegtyar
55fbc1a355
Uncomment sat command in memory.ys test.
2019-09-03 12:11:12 +03:00
SergeyDegtyar
11f330ed22
Add tests for ECP5 architecture
2019-09-03 11:53:37 +03:00
Emily
69a5dea89e
Use `command -v` rather than `which`
2019-09-03 00:57:32 +01:00
Eddie Hung
2fa3857963
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-02 12:13:44 -07:00
Eddie Hung
4aa505d1b2
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
...
ice40_dsp to allow signed multipliers
2019-09-01 10:11:33 -07:00
Eddie Hung
4290548de3
Make abc9 test a bit more interesting
2019-08-30 20:31:53 -07:00
Eddie Hung
9be9631e5a
Add macc test, with equiv_opt not currently passing
2019-08-30 16:18:14 -07:00
Eddie Hung
d508dc2906
Update test for ffM
2019-08-30 15:01:08 -07:00
Eddie Hung
7df0e77565
Add mul_unsigned test
2019-08-30 14:35:05 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
...
abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
76a52712da
Improve tests/ice40/macc.ys for SB_MAC16
2019-08-30 12:22:59 -07:00
Eddie Hung
eef0676105
Merge pull request #1310 from SergeyDegtyar/master
...
Add new tests for ice40 architecture
2019-08-30 10:54:22 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
SergeyDegtyar
53912ad649
macc test fix
2019-08-30 16:01:36 +03:00
SergeyDegtyar
17c92dc679
Fix macc test
2019-08-30 15:22:46 +03:00
SergeyDegtyar
94a56c14b7
div_mod test fix
2019-08-30 14:17:03 +03:00
SergeyDegtyar
f4a48ce8e6
fix div_mod test
2019-08-30 13:22:11 +03:00
SergeyDegtyar
86f1375ecd
Fix test for counter
2019-08-30 12:38:28 +03:00
Sergey
f23b540b45
Merge branch 'master' into master
2019-08-30 10:29:47 +03:00
SergeyDegtyar
d144748401
Add new tests.
2019-08-30 09:45:33 +03:00
SergeyDegtyar
eb0a5b2293
Remove unnecessary common.v(assertions for testbenches).
2019-08-30 09:17:32 +03:00
SergeyDegtyar
8e3abda193
Remove simulation from run-test.sh (unnecessary paths)
2019-08-30 09:11:03 +03:00
SergeyDegtyar
20f4aea480
Remove simulation from run-test.sh
2019-08-30 08:53:35 +03:00
Eddie Hung
6a111ad324
Nicer formatting
2019-08-29 17:24:48 -07:00
Sergey
d360693040
Merge pull request #3 from YosysHQ/Sergey/tests_ice40
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Merge my changes to tests_ice40 branch
2019-08-29 21:07:34 +03:00
Eddie Hung
67587bad7f
Add constant expression attribute to test
2019-08-29 09:10:20 -07:00
SergeyDegtyar
d588c6898f
Add comments for examples from Lattice user guide
2019-08-29 10:49:46 +03:00
Eddie Hung
1fdb3fc98c
Add failing test
2019-08-28 19:58:58 -07:00
Eddie Hung
13ecd8b0df
Add run-test.sh too
2019-08-28 18:47:48 -07:00
Eddie Hung
e301a3dadb
Add SB_CARRY to ice40_opt test
2019-08-28 18:46:53 -07:00
Eddie Hung
dd42aa87b9
Add ice40_opt test
2019-08-28 18:46:53 -07:00
Eddie Hung
b8a9f73089
Comment out *.sh used for testbenches as we have no more
2019-08-28 12:36:20 -07:00
Eddie Hung
87d5d9b8c8
Use equiv for memory and dpram
2019-08-28 12:30:35 -07:00
Eddie Hung
ebd0a1875b
Use equiv_opt for latches
2019-08-28 12:21:15 -07:00
Eddie Hung
32eef26ee2
Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
2019-08-28 12:18:32 -07:00
Eddie Hung
64ea147236
Add .gitignore
2019-08-28 09:55:34 -07:00
Eddie Hung
2f493fb465
Use test_pmgen for xilinx_srl
2019-08-28 09:55:09 -07:00
Eddie Hung
2e9e745efa
Do not simplemap for variable test
2019-08-28 09:26:08 -07:00
Eddie Hung
975aaf190f
Add xilinx_srl test
2019-08-28 09:24:19 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
SergeyDegtyar
fe58790f37
Revert "Add tests for ecp5"
...
This reverts commit 2270ead09f
.
2019-08-28 09:49:58 +03:00
SergeyDegtyar
2270ead09f
Add tests for ecp5
2019-08-28 09:47:03 +03:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init
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In sat: 'x' in init attr should be ignored
2019-08-28 00:18:14 +02:00
Eddie Hung
00387f3927
Revert to using clean
2019-08-27 09:24:32 -07:00
SergeyDegtyar
980830f7b8
Revert "Add tests for ecp5 architecture."
...
This reverts commit 134d3fea90
.
2019-08-27 18:28:05 +03:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
SergeyDegtyar
134d3fea90
Add tests for ecp5 architecture.
2019-08-27 18:12:18 +03:00
SergeyDegtyar
aad9bad326
Add tests for macc and rom;
...
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 ;
In both cases synthesized only LUTs and DFFs.
2019-08-27 13:56:26 +03:00
Eddie Hung
6b5e65919a
Revert "In sat: 'x' in init attr should not override constant"
...
This reverts commit 2b37a093e9
.
2019-08-26 17:52:57 -07:00
Eddie Hung
528f1c8687
Improve tests to check that clkbuf is connected to expected
2019-08-26 13:45:16 -07:00
Eddie Hung
dc87372a97
Wire with init on FF part, 1'bx on non-FF part
2019-08-24 15:05:44 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
a0d85393e3
Check clkbuf_inhibit=1 is ignored for custom selection
2019-08-23 11:15:26 -07:00
Eddie Hung
5628e2ec53
Add simple clkbufmap tests
2019-08-23 11:10:02 -07:00
Eddie Hung
d62c10d641
tests/techmap/run-test.sh to cope with *.ys
2019-08-23 11:09:50 -07:00
Eddie Hung
10c41a5cf5
Blocking assignment
2019-08-23 09:11:04 -07:00
SergeyDegtyar
c29380b381
Fix pull request
2019-08-23 18:55:01 +03:00
SergeyDegtyar
3c10f58d04
Fix run-test.sh; Add new test for dpram.
2019-08-23 17:00:16 +03:00
SergeyDegtyar
0b25dbf1c6
Fix path in run-test.sh
2019-08-23 12:40:14 +03:00
Eddie Hung
fe1b2337fd
Do not propagate mem2reg attribute through to result
2019-08-22 16:57:59 -07:00
Eddie Hung
36cf0a3dd5
Remove adffs_tb.v
2019-08-22 16:50:14 -07:00
Eddie Hung
51ffb093b5
In sat: 'x' in init attr should not override constant
2019-08-22 16:43:08 -07:00
Eddie Hung
2b37a093e9
In sat: 'x' in init attr should not override constant
2019-08-22 16:42:19 -07:00
Eddie Hung
66607845ec
Remove Xilinx test
2019-08-22 16:18:07 -07:00
Eddie Hung
e7a8cdbccf
Add shregmap -tech xilinx test
2019-08-22 16:16:54 -07:00
Eddie Hung
698a0e3aaf
WIP for equivalency checking memories
2019-08-22 16:05:12 -07:00
Eddie Hung
43e7c4917a
Do not print OKAY
2019-08-22 16:05:12 -07:00
Eddie Hung
5061d239ae
Fail if iverilog fails
2019-08-22 16:05:12 -07:00
Eddie Hung
8e3754bdb4
Hide tri-state warning message for now
2019-08-22 16:05:12 -07:00
Eddie Hung
659a481482
Remove unused output
2019-08-22 16:05:12 -07:00
Eddie Hung
61087329ef
Fix tribuf test
2019-08-22 16:05:12 -07:00
Eddie Hung
f9906eed68
Fix comments
2019-08-22 16:05:12 -07:00
Eddie Hung
9224b3bc17
Remove tech independent synthesis
2019-08-22 16:05:12 -07:00
Eddie Hung
388eb3288c
Remove dffe instantation
2019-08-22 16:04:50 -07:00
Eddie Hung
9e537a76b5
Move $dffe to dffs.{v,ys}
2019-08-22 16:04:48 -07:00
Eddie Hung
c5754d9e8b
Make multiplier wider, do not do tech independent synth
2019-08-22 16:04:07 -07:00
Eddie Hung
b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
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opt_expr to trim A port of $shiftx/$shift
2019-08-22 10:31:27 -07:00
Eddie Hung
6f971470f8
Respect opt_expr -keepdc as per @cliffordwolf
2019-08-22 08:37:27 -07:00
Eddie Hung
379f33af54
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
2019-08-22 08:22:23 -07:00
Eddie Hung
bb1a8a0190
Add test
2019-08-21 21:58:20 -07:00
Eddie Hung
a6776ee35e
mem2reg to preserve user attributes and src
2019-08-21 13:36:01 -07:00
SergeyDegtyar
d945b8a357
Fix all comments from PR
2019-08-21 21:52:07 +03:00
SergeyDegtyar
b835ec37cb
Add temp directory
2019-08-21 07:53:34 +03:00
Eddie Hung
fce8dc7db2
Add test
2019-08-20 20:05:16 -07:00
SergeyDegtyar
71dd412ac5
Fix tests; Remove simulation;
...
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
2019-08-20 15:52:25 +03:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen
2019-08-20 11:39:23 +02:00
Clifford Wolf
6ffb910d12
Add test case for real parameters
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-20 11:38:21 +02:00
SergeyDegtyar
153ec0541c
Add new tests for ice40 architecture
2019-08-20 07:50:05 +03:00
whitequark
4a942ba7b9
proc_clean: fix order of switch insertion.
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Fixes #1268 .
2019-08-19 16:44:23 +00:00
Clifford Wolf
21699e5840
Add *.sv to tests/simple_abc9/.gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-19 13:04:57 +02:00
Clifford Wolf
1e3dd0a2da
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
2019-08-19 13:04:06 +02:00
Eddie Hung
e34f2de55d
Merge remote-tracking branch 'origin/master' into clifford/testfast
2019-08-18 21:29:15 -07:00
Eddie Hung
f5170a7eda
Removal of more `stat` calls from tests
2019-08-18 21:28:45 -07:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Clifford Wolf
9e940f1276
Speed up "make test" and related cleanups
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:37:07 +02:00
Clifford Wolf
f20be90436
Add test for pmtest_test "reduce" demo pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:05:10 +02:00
Eddie Hung
51d28645da
Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share
2019-08-16 13:40:29 -07:00
Clifford Wolf
40c40d9f5d
Do not use Verific in tests/various/write_gzip.ys
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:22:46 +02:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
...
This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
Eddie Hung
88d5185596
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
2019-08-11 21:13:40 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Eddie Hung
0adf81cb91
Add $alu tests
2019-08-09 12:13:17 -07:00
Eddie Hung
8350dfb809
Add alumacc versions of opt_expr tests
2019-08-09 10:30:53 -07:00
Eddie Hung
9300111601
Add new $alu test, remove wreduce
2019-08-09 10:22:06 -07:00
Eddie Hung
313c9ec8df
Cleanup some more
2019-08-09 10:13:49 -07:00
Eddie Hung
d9c1664462
Simplify opt_expr tests using equiv_opt
2019-08-09 10:08:17 -07:00
Eddie Hung
8bf45f34c4
Remove dump call
2019-08-07 21:36:02 -07:00
Eddie Hung
2b6cdfb39f
Move tests/various/opt* into tests/opt/
2019-08-07 21:35:48 -07:00
Eddie Hung
d5e8c0e6d3
Remove ice40_unlut call, simply do equiv_opt on synth_ice40
2019-08-07 21:33:56 -07:00
Eddie Hung
35bf509603
Add testcase from removed opt_ff.{v,ys}
2019-08-07 21:31:32 -07:00
Eddie Hung
4545bf482f
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
2019-08-07 16:48:38 -07:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
Bogdan Vukobratovic
067b44938c
Fix wrong results when opt_share called before opt_clean
2019-08-07 09:30:58 +02:00
Eddie Hung
2d1b517b01
Add signed opt_expr tests
2019-08-06 15:40:30 -07:00
Eddie Hung
769c750c22
Add signed test
2019-08-06 15:38:43 -07:00
Eddie Hung
51b39219cd
Move LSB tests from wreduce to opt_expr
2019-08-06 15:24:49 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
David Shah
3a3da678ad
Add test for writing gzip-compressed files
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 17:43:04 +01:00
Bogdan Vukobratovic
6a796accc0
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic
d8be5ce6ba
Tabs to spaces in opt_share examples
2019-08-03 12:35:46 +02:00
Bogdan Vukobratovic
280c4e7794
Fix spacing in opt_share tests, change wording in opt_share help
2019-08-03 12:28:46 +02:00
Jim Lawson
3b8c917025
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
...
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
...
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
David Shah
933db0410e
Add support for reading gzip'd input files
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
Eddie Hung
c926eeb43a
Add another test
2019-07-19 14:02:46 -07:00
Eddie Hung
5bd088a686
Add one more test with trimming Y_WIDTH of $sub
2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df
Be more explicit
2019-07-19 12:53:18 -07:00
Eddie Hung
4e9b1d36fa
Add tests for sub too
2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2
Add test
2019-07-19 12:43:02 -07:00
Eddie Hung
8a2a2cd035
Forgot to commit
2019-07-16 12:44:26 -07:00
Eddie Hung
dd10d2b00d
Add tests for cmp2lut on LUT6
2019-07-16 12:11:59 -07:00
Eddie Hung
41243a53b3
Update test with more accurate LUT mask
2019-07-12 21:00:59 -07:00
Clifford Wolf
9546ccdbd3
Fix tests/various/async FFL test
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Clifford Wolf
5138621482
Improve tests/various/async, disable failing ffl test
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:21:25 +02:00
Clifford Wolf
c18b23f055
Add tests/various/async.{sh,v}
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:59 +02:00
Clifford Wolf
3dd92fcd15
Improve tests/various/run-test.sh
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:28 +02:00
Clifford Wolf
f8512864cd
Add tests/simple_abc9/.gitignore
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:01 +02:00
Eddie Hung
de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
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write_xaiger to treat unknown cell connections as keep-s
2019-07-03 09:43:00 -07:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
...
Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf
1f173210eb
Fix tests/various/specify.v
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:25:05 +02:00
Clifford Wolf
ba36567908
Some cleanups in "ignore specify parser"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Eddie Hung
9c556e3c02
Add test
2019-07-02 19:13:40 -07:00
Eddie Hung
8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire
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Add "script -select [selection]" to allow commands to be taken from wires
2019-07-02 10:20:42 -07:00
Eddie Hung
81a717e9b7
Update test for Pass::call_on_module()
2019-07-02 08:22:31 -07:00
Eddie Hung
90382a0f6d
Update test too
2019-07-02 08:19:23 -07:00
David Shah
d45936fe5f
memory_dff: Fix checking of feedback mux input when more than one mux
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Eddie Hung
04459cb30a
Comment out invalid syntax
2019-06-30 11:48:01 -07:00
Eddie Hung
fd2fb4f0f0
Merge branch 'master' into eddie/script_from_wire
2019-06-28 14:56:34 -07:00
Eddie Hung
0ec7c09756
autotest.sh to define _AUTOTB when test_autotb
2019-06-28 14:56:22 -07:00
Eddie Hung
64f6b0c747
Try command in another module
2019-06-28 13:41:32 -07:00
Eddie Hung
2c6aaef3db
Add test
2019-06-28 13:32:09 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
...
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung
dc677c791d
Add test from #1144 , and try reading without '-specify' flag
2019-06-28 10:12:48 -07:00
Clifford Wolf
74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext
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tests: use optional ABCEXTERNAL when specified
2019-06-28 10:30:31 +02:00
Clifford Wolf
1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
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Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Gabriel L. Somlo
6f1c137989
tests: use optional ABCEXTERNAL when specified
...
Commits 65924fd1
, abc40924
, and ebe29b66
hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-27 23:00:13 -04:00
Eddie Hung
9a371cfba9
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 12:53:23 -07:00
Eddie Hung
c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
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tests: Check that Icarus can parse arch sim models
2019-06-27 12:31:15 -07:00
Eddie Hung
440f173aef
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 11:54:34 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
...
Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
ab7c431905
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
Eddie Hung
18acb72c05
Add #1135 testcase
2019-06-27 11:02:52 -07:00
Eddie Hung
3910bc2ea6
Copy tests from eddie/fix1132
2019-06-27 06:01:50 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
David Shah
71b046d639
tests: Check that Icarus can parse arch sim models
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Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 18:46:22 +01:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Eddie Hung
ab6e8ce0f0
Add testcase from #335 , fixed by #1130
2019-06-25 08:43:58 -07:00
Clifford Wolf
add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
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memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung
9dca024a30
Add tests/various/abc9.{v,ys} with SCC test
2019-06-24 21:52:53 -07:00
Eddie Hung
a701a2accf
Add test
2019-06-24 18:32:58 -07:00
Eddie Hung
4ddc0354c1
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-22 14:40:55 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
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Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung
32f637ffdb
Add more tests
2019-06-21 12:31:04 -07:00
Eddie Hung
ae8305ffcc
Fix testcase
2019-06-21 12:13:00 -07:00
Eddie Hung
6ec8160981
Add more muxpack tests, with overlapping entries
2019-06-21 11:45:53 -07:00
Eddie Hung
63eb5cace9
Merge branch 'master' into eddie/muxpack
2019-06-21 11:17:19 -07:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
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Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118
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Make genvar a signed type
2019-06-21 10:13:13 +02:00
Eddie Hung
844c42cef8
Missing a `clean` and `opt_expr -mux_bool` in test
2019-06-20 19:47:59 -07:00
Eddie Hung
75375a3fbc
Add test
2019-06-20 19:47:59 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
014606affe
Fix issue with part of PI being 1'bx
2019-06-20 17:38:16 -07:00
Eddie Hung
c20adc5263
Add test
2019-06-20 16:07:22 -07:00
Eddie Hung
d0bbf9e4d4
Extend sign extension tests
2019-06-20 12:43:59 -07:00
Eddie Hung
b77322034c
Remove leftover comment
2019-06-20 10:15:04 -07:00
Eddie Hung
b98276fa61
Add test
2019-06-20 10:13:52 -07:00
Clifford Wolf
a8c85d1b4b
Update some .gitignore files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 14:27:57 +02:00
Clifford Wolf
2454ad99bf
Refactor "opt_rmdff -sat"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
6a6dd5e057
Add proper test for SV-style arrays
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:06:07 +02:00
Clifford Wolf
2428fb7dc2
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays
2019-06-20 12:03:00 +02:00
Clifford Wolf
5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
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Improve handling of initial/default values
2019-06-19 13:53:07 +02:00
Tobias Wölfel
8b8af10f5e
Unpacked array declaration using size
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Allows fixed-sized array dimension specified by a single number.
This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560 .
But is split out of the original work.
2019-06-19 12:47:48 +02:00
Clifford Wolf
c330379870
Make tests/aiger less chatty
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:20:35 +02:00
Clifford Wolf
fa5fc3f6af
Add defvalue test, minor autotest fixes for .sv files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:12:08 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Eddie Hung
9f275c1437
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 16:33:05 -07:00
Eddie Hung
2e7b3eee40
Add a couple more tests
2019-06-12 15:43:43 -07:00
Eddie Hung
2cbcd6224c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
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This reverts commit a138381ac3
, reversing
changes made to b77c5da769
.
2019-06-12 09:05:02 -07:00
Eddie Hung
86efe9a616
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 09:01:15 -07:00
Eddie Hung
45c2a5f876
Add shregmap -tech xilinx test
2019-06-12 08:34:06 -07:00
Eddie Hung
a138381ac3
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-10 16:21:43 -07:00
Eddie Hung
c314ca3c51
Add test
2019-06-10 16:16:26 -07:00
Eddie Hung
352c532bb2
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-10 11:02:54 -07:00
Eddie Hung
1dd7e23a20
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-10 10:28:40 -07:00
Eddie Hung
a91ea6612a
Add some more comments
2019-06-10 10:27:55 -07:00
Eddie Hung
1e201a9b01
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-07 16:15:19 -07:00
Eddie Hung
58f4b106f3
Merge branch 'master' into eddie/muxpack
2019-06-07 15:47:28 -07:00
Eddie Hung
b959bf79c0
Add nonexcl case test, comment out two others
2019-06-07 15:35:15 -07:00
Eddie Hung
1da12c5071
Add @cliffordwolf freduce testcase
2019-06-07 12:12:11 -07:00
Eddie Hung
e263bc249b
Add nonexclusive test from @cliffordwolf
2019-06-07 11:54:29 -07:00
Eddie Hung
65924fd12f
Test *.aag too, by using *.aig as reference
2019-06-07 11:28:05 -07:00
Eddie Hung
abc40924ed
Use ABC to convert from AIGER to Verilog
2019-06-07 11:06:57 -07:00
Eddie Hung
ebe29b6659
Use ABC to convert AIGER to Verilog, then sat against Yosys
2019-06-07 11:05:36 -07:00
Eddie Hung
1b113a0574
Add symbols to AIGER test inputs for ABC
2019-06-07 11:05:25 -07:00
Eddie Hung
0f6e914ef6
Another muxpack test
2019-06-07 08:34:58 -07:00
Clifford Wolf
6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983
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elaboration system tasks
2019-06-07 13:39:46 +02:00
Clifford Wolf
f01a61f093
Rename implicit_ports.sv test to implicit_ports.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 13:12:25 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f
Cleanup tux3-implicit_named_connection
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
2019-06-07 11:41:54 +02:00
Eddie Hung
2223ca91b0
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:22:10 -07:00
Eddie Hung
5c277c6325
Fix and test for balanced case
2019-06-06 14:21:34 -07:00
Eddie Hung
eaee250a6e
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:06:59 -07:00
Eddie Hung
0a66720f6f
Fix warnings
2019-06-06 14:01:42 -07:00
Eddie Hung
ccdf989025
Support cascading $pmux.A with $mux.A and $mux.B
2019-06-06 13:51:22 -07:00
Eddie Hung
705388eb24
Add non exclusive test
2019-06-06 12:44:06 -07:00
Eddie Hung
b8620f7b3d
One more and tidy up
2019-06-06 12:03:44 -07:00
Eddie Hung
5d4eca5a29
Add a few more special case tests
2019-06-06 11:59:41 -07:00
Eddie Hung
3e76e3a6fa
Add tests, fix for !=
2019-06-06 11:54:38 -07:00
tux3
88f5977093
SystemVerilog support for implicit named port connections
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This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Maciej Kurc
b79bd5b3ca
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-04 10:42:42 +02:00
Eddie Hung
f81a0ed92e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-03 23:07:08 -07:00
Maciej Kurc
5739cf5265
Added tests for attributes
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-03 09:25:20 +02:00
Eddie Hung
25befbf542
Rename to #23
2019-05-29 15:26:33 -07:00
Eddie Hung
aa2380c17a
Add abc_test024
2019-05-29 15:24:38 -07:00
Eddie Hung
92197326b8
Add abc9_test022
2019-05-28 12:43:07 -07:00
Clifford Wolf
349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047
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Do not use shiftmul peepopt pattern when mul result is truncated
2019-05-28 19:02:26 +02:00
Eddie Hung
5f39c262c2
From master
2019-05-28 09:38:58 -07:00
Eddie Hung
ba9513b325
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-28 09:30:53 -07:00
Clifford Wolf
cb285e4b87
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 17:17:56 +02:00
Clifford Wolf
e3ebac44df
Add actual wandwor test that is part of "make test"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:42:50 +02:00
Bogdan Vukobratovic
9a468f81c4
Optimizing DFFs whose initial value prevents their value from changing
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This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
2019-05-28 08:48:21 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
f68b658b4b
reformat wand/wor test
2019-05-27 18:45:54 +02:00
Stefan Biereigel
c5fe04acfd
remove port direction workaround from test case
2019-05-27 18:10:39 +02:00
Eddie Hung
f3e86e06e6
Fix init
2019-05-24 18:43:26 -07:00
Eddie Hung
e1cb1bb948
Fix typos
2019-05-24 18:34:27 -07:00
Eddie Hung
d15da4bc11
Add more tests
2019-05-24 18:33:18 -07:00
Eddie Hung
4bd9465ed3
Call proc
2019-05-24 18:32:02 -07:00
Eddie Hung
f0c6b73b72
Fix duplicate driver
2019-05-24 17:44:57 -07:00
Eddie Hung
68359bcd6f
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
2019-05-23 13:37:53 -07:00
Eddie Hung
47f9ea142f
Add opt_rmdff tests
2019-05-23 11:26:38 -07:00
Stefan Biereigel
c2caf85f7c
add simple test case for wand/wor
2019-05-23 13:57:27 +02:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Maciej Kurc
1f52332b8d
Added tests for Verilog frontent for attributes on parameters and localparams
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00
Clifford Wolf
b7ec698d40
Add test case from #997
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:58:04 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00