mirror of https://github.com/YosysHQ/yosys.git
Add one more test with trimming Y_WIDTH of $sub
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@ -9,7 +9,7 @@ hierarchy -auto-top
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proc
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design -save gold
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prep
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prep # calls wreduce
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select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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@ -21,8 +21,8 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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### X - 0
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read_verilog <<EOT
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module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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@ -33,7 +33,7 @@ hierarchy -auto-top
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proc
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design -save gold
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prep
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prep # calls wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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@ -45,9 +45,10 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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### 0 - X
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##########
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read_verilog <<EOT
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module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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@ -56,7 +57,7 @@ hierarchy -auto-top
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proc
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design -save gold
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prep
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prep # calls wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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@ -68,10 +69,11 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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### 0 - X
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##########
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read_verilog <<EOT
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module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (j >> 4) - i;
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endmodule
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EOT
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@ -79,9 +81,10 @@ hierarchy -auto-top
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proc
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design -save gold
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prep
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prep # calls wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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dump
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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