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This commit is contained in:
Eddie Hung 2019-07-19 12:53:18 -07:00
parent fc0e36d1c0
commit 415a2716df
1 changed files with 29 additions and 6 deletions
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35
tests/various/wreduce.ys
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@ -1,6 +1,6 @@
read_verilog <<EOT
module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
module wreduce_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) + j;
endmodule
EOT
@ -11,7 +11,7 @@ design -save gold
prep
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
@ -24,7 +24,7 @@ sat -verify -prove-asserts -show-ports miter
### X - 0
read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = j - (i << 4);
endmodule
EOT
@ -35,7 +35,7 @@ design -save gold
prep
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 %i %i
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
@ -47,7 +47,7 @@ sat -verify -prove-asserts -show-ports miter
### 0 - X
read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) - j;
endmodule
EOT
@ -58,7 +58,30 @@ design -save gold
prep
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 %i %i
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
### 0 - X
read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) - j;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -stash gate