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Call proc
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@ -2,12 +2,12 @@ read_verilog -icells opt_rmdff.v
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prep
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design -stash gold
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read_verilog -icells opt_rmdff.v
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proc
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opt_rmdff
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select -assert-count 0 c:remove*
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select -assert-min 7 c:keep*
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prep
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design -stash gate
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design -import gold -as gold
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