riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add nonexclusive test from @cliffordwolf

This commit is contained in:
Eddie Hung 2019-06-07 11:54:29 -07:00
parent 887df8914c
commit e263bc249b
2 changed files with 28 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
tests/various/muxpack.v
View File

@ -153,3 +153,16 @@ always @*
else
o <= i[4*W+:W];
endmodule
module cliffordwolf_nonexclusive_select (
input wire x, y, z,
input wire a, b, c, d,
output reg o
);
always @* begin
o = a;
if (x) o = b;
if (y) o = c;
if (z) o = d;
end
endmodule

15
tests/various/muxpack.ys
View File

@ -163,3 +163,18 @@ design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top cliffordwolf_nonexclusive_select
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter