Add test

tests/various/script.ys

@@ -0,0 +1,17 @@
+read_verilog -formal <<EOT
+    module top;
+        foo bar();
+        foo asdf();
+        winnie the_pooh();
+
+        wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
+        wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
+        wire [1023:0] _DELETE = "delete c:bar";
+    endmodule
+EOT
+
+script -select w:_RUNME*
+
+select w:_DELETE
+script -select
+select -assert-count 1 t:foo