mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
write_xaiger to treat unknown cell connections as keep-s
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commit
de26328130
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@ -138,6 +138,7 @@ struct XAigerWriter
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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pool<SigBit> keep_bits;
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// promote public wires
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for (auto wire : module->wires())
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@ -168,6 +169,9 @@ struct XAigerWriter
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unused_bits.insert(bit);
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}
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if (keep)
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keep_bits.insert(bit);
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if (wire->port_input || keep) {
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if (bit != wirebit)
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alias_map[bit] = wirebit;
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@ -235,7 +239,7 @@ struct XAigerWriter
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log_assert(!holes_mode);
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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if (!holes_mode) {
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@ -255,10 +259,11 @@ struct XAigerWriter
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}
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}
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else {
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bool cell_known = cell->known();
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for (const auto &c : cell->connections()) {
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if (c.second.is_fully_const()) continue;
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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auto is_input = !cell_known || cell->input(c.first);
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auto is_output = !cell_known || cell->output(c.first);
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if (!is_input && !is_output)
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log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
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@ -266,12 +271,15 @@ struct XAigerWriter
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for (auto b : c.second.bits()) {
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Wire *w = b.wire;
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if (!w) continue;
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if (!w->port_output) {
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if (!w->port_output || !cell_known) {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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output_bits.insert(b);
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unused_bits.erase(b);
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if (!cell_known)
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keep_bits.insert(b);
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}
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}
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}
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@ -424,7 +432,7 @@ struct XAigerWriter
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auto jt = input_bits.find(b);
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if (jt != input_bits.end()) {
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log_assert(b.wire->attributes.count("\\keep"));
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log_assert(keep_bits.count(O));
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input_bits.erase(b);
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}
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}
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@ -444,7 +452,7 @@ struct XAigerWriter
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// with $inout.out suffix, make it a PO driven by the existing inout, and
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// inherit existing inout's drivers
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if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
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|| wire->attributes.count("\\keep")) {
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|| keep_bits.count(bit)) {
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RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
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RTLIL::Wire *new_wire = module->wire(wire_name);
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if (!new_wire)
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@ -3,3 +3,7 @@ initial o = 1'b0;
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always @*
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o <= ~o;
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endmodule
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module abc9_test028(input i, output o);
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unknown u(~i, o);
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endmodule
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@ -1,4 +1,6 @@
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read_verilog abc9.v
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design -save read
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hierarchy -top abc9_test027
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proc
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design -save gold
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@ -12,3 +14,11 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top abc9_test028
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proc
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abc9 -lut 4
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select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i
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select -assert-count 1 t:unknown
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select -assert-none t:$lut t:unknown %% t: %D
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