Add shregmap -tech xilinx test

2019-06-12 08:34:06 -07:00 · 2019-06-12 08:34:06 -07:00 · e7a8cdbccf
parent 8691596d19
commit e7a8cdbccf
1 changed files with 1 additions and 0 deletions
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter

 # design -load gate
 # stat
+