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Merge branch 'master' into master
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Sergey
GitHub
commit
f23b540b45
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@ -3,11 +3,11 @@
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# NB: Inputs/Outputs must be ordered alphabetically
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# (with exceptions for carry in/out)
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# Inputs: A B CI
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# Inputs: A B I0 I3 CI
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# Outputs: O CO
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# (NB: carry chain input/output must be last
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# input/output and have been moved there
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# overriding the alphabetical ordering)
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$__ICE40_FULL_ADDER 1 1 3 2
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400 379 316
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259 231 126
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$__ICE40_CARRY_WRAPPER 1 1 5 2
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400 379 449 316 316
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259 231 - - 126
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@ -3,11 +3,11 @@
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# NB: Inputs/Outputs must be ordered alphabetically
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# (with exceptions for carry in/out)
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# Inputs: A B CI
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# Inputs: A B I0 I3 CI
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# Outputs: O CO
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# (NB: carry chain input/output must be last
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# input/output and have been moved there
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# overriding the alphabetical ordering)
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$__ICE40_FULL_ADDER 1 1 3 2
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589 558 465
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675 609 186
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$__ICE40_CARRY_WRAPPER 1 1 5 2
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589 558 661 465 465
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675 609 - - 186
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@ -3,11 +3,11 @@
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# NB: Inputs/Outputs must be ordered alphabetically
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# (with exceptions for carry in/out)
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# Inputs: A B CI
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# Inputs: A B I0 I3 CI
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# Outputs: O CO
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# (NB: carry chain input/output must be last
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# input/output and have been moved there
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# overriding the alphabetical ordering)
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$__ICE40_FULL_ADDER 1 1 3 2
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1231 1205 874
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675 609 278
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$__ICE40_CARRY_WRAPPER 1 1 5 2
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1231 1205 1285 874 874
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675 609 - - 278
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@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
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endmodule
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(* abc_box_id = 1, lib_whitebox *)
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module \$__ICE40_FULL_ADDER (
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module \$__ICE40_CARRY_WRAPPER (
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(* abc_carry *)
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output CO,
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output O,
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input A,
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input B,
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input A, B,
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(* abc_carry *)
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input CI
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input CI,
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input I0, I3
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);
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parameter LUT = 0;
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
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.CO(CO)
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);
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SB_LUT4 #(
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// I0: 1010 1010 1010 1010
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// I1: 1100 1100 1100 1100
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// I2: 1111 0000 1111 0000
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// I3: 1111 1111 0000 0000
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.LUT_INIT(16'b 0110_1001_1001_0110)
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.LUT_INIT(LUT)
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) adder (
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.I0(1'b0),
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.I0(I0),
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.I1(A),
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.I2(B),
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.I3(CI),
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.I3(I3),
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.O(O)
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);
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endmodule
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@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
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continue;
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}
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if (cell->type == "$__ICE40_FULL_ADDER")
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if (cell->type == "$__ICE40_CARRY_WRAPPER")
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{
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SigSpec non_const_inputs, replacement_output;
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int count_zeros = 0, count_ones = 0;
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@ -114,16 +114,17 @@ static void run_ice40_opts(Module *module)
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optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
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module->connect(cell->getPort("\\CO")[0], replacement_output);
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
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log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
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log_id(module), log_id(cell), log_signal(replacement_output));
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cell->type = "$lut";
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cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
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cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
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cell->setPort("\\Y", cell->getPort("\\O"));
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cell->unsetPort("\\B");
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cell->unsetPort("\\CI");
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I3");
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cell->unsetPort("\\CO");
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cell->unsetPort("\\O");
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cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
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cell->setParam("\\WIDTH", 4);
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}
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continue;
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@ -0,0 +1,26 @@
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read_verilog -icells -formal <<EOT
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module top(input CI, I0, output [1:0] CO, output O);
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wire A = 1'b0, B = 1'b0;
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\$__ICE40_CARRY_WRAPPER #(
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// A[0]: 1010 1010 1010 1010
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// A[1]: 1100 1100 1100 1100
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// A[2]: 1111 0000 1111 0000
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// A[3]: 1111 1111 0000 0000
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.LUT(~16'b 0110_1001_1001_0110)
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) u0 (
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.A(A),
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.B(B),
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.CI(CI),
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.I0(I0),
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.I3(CI),
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.CO(CO[0]),
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.O(O)
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);
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SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
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endmodule
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EOT
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equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
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design -load postopt
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select -assert-count 1 t:*
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select -assert-count 1 t:$lut
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