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Improve tests/various/async, disable failing ffl test 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-07-09 22:21:25 +02:00
parent c18b23f055
commit 5138621482
2 changed files with 38 additions and 7 deletions
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9
tests/various/async.sh
View File

@ -1,6 +1,11 @@
#!/bin/bash
set -ex
../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v
iverilog -o async_sim -DTESTBENCH async.v async_syn.v
../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v
../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v
../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v
iverilog -o async_sim -DTESTBENCH async.v async_???.v
vvp -N async_sim > async.out
rm -f async_syn.v async_sim async.out async.vcd
tail async.out
grep PASS async.out
rm -f async_???.v async_sim async.out async.vcd

36
tests/various/async.v
View File

@ -32,9 +32,23 @@ module uut (
endmodule
`ifdef TESTBENCH
module \$ff #(
parameter integer WIDTH = 1
) (
input [WIDTH-1:0] D,
output reg [WIDTH-1:0] Q
);
wire sysclk = testbench.sysclk;
always @(posedge sysclk)
Q <= D;
endmodule
module testbench;
reg sysclk;
always #5 sysclk = (sysclk === 1'b0);
reg clk;
always #5 clk = (clk === 1'b0);
always @(posedge sysclk) clk = (clk === 1'b0);
reg d, r, e;
@ -44,13 +58,25 @@ module testbench;
wire [`MAXQ:0] q_syn;
syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn));
wire [`MAXQ:0] q_prp;
prp prp (.clk(clk), .d(d), .r(r), .e(e), .q(q_prp));
wire [`MAXQ:0] q_a2s;
a2s a2s (.clk(clk), .d(d), .r(r), .e(e), .q(q_a2s));
wire [`MAXQ:0] q_ffl;
ffl ffl (.clk(clk), .d(d), .r(r), .e(e), .q(q_ffl));
task printq;
reg [5*8-1:0] msg;
begin
msg = "OK";
if (q_uut != q_syn) msg = "SYN";
$display("%6t %b %b %s", $time, q_uut, q_syn, msg);
if (msg != "OK") $stop;
if (q_uut !== q_syn) msg = "SYN";
if (q_uut !== q_prp) msg = "PRP";
if (q_uut !== q_a2s) msg = "A2S";
// if (q_uut !== q_ffl) msg = "FFL";
$display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg);
if (msg != "OK") $finish;
end
endtask
@ -75,7 +101,7 @@ module testbench;
r <= $random;
e <= $random;
end
$display("OK");
$display("PASS");
$finish;
end
endmodule