riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanup some more

This commit is contained in:
Eddie Hung 2019-08-09 10:13:49 -07:00
parent d9c1664462
commit 313c9ec8df
1 changed files with 0 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
tests/opt/opt_expr.ys
View File

@ -5,8 +5,6 @@ module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
endmodule
EOT
hierarchy -auto-top
equiv_opt -assert opt_expr -fine
design -load postopt
@ -22,8 +20,6 @@ module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, outp
endmodule
EOT
hierarchy -auto-top
equiv_opt -assert opt_expr -fine
design -load postopt
@ -39,8 +35,6 @@ module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
endmodule
EOT
hierarchy -auto-top
equiv_opt -assert opt_expr -fine
design -load postopt
@ -56,8 +50,6 @@ module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, out
endmodule
EOT
hierarchy -auto-top
equiv_opt -assert opt_expr -fine
design -load postopt
@ -73,8 +65,6 @@ module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
endmodule
EOT
hierarchy -auto-top
equiv_opt -assert opt_expr -fine
design -load postopt
@ -90,8 +80,6 @@ module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
endmodule
EOT
hierarchy -auto-top
equiv_opt -assert opt_expr -fine
design -load postopt