mirror of https://github.com/YosysHQ/yosys.git
remove port direction workaround from test case
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@ -17,7 +17,6 @@ module c;
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wand E;
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wire E_wire = E;
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genvar i;
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for (i = 0; i < 3; i = i + 1)
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@ -27,7 +26,7 @@ module c;
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);
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b b_inst (
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.D(E_wire)
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.D(E)
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);
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end
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